Flip-flops

• US 6,333,656 B1
• Filed: 03/22/2000
• Issued: 12/25/2001
• Est. Priority Date: 11/25/1998
• Status: Expired due to Fees

• Current Assignee: Innurvation IP LLC
• Original Assignee: Nanopower Technologies, Inc.
• Inventors: Schober, Robert C.
• Primary Examiner(s): LAM, TUAN THIEU
• Application Number:
  US09/528,966
• Time in Patent Office: 643 Days
• Field of Search: 327/202, 327/203, 327/208-212, 327/218
• US Class Current: 327/202
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H03K 19/215 using field-effect transistors
• CPC Class Codes: H03K 19/23 Majority or minority circuits, i.e. giving output having the state of the majority or the minority of the inputs
• CPC Class Codes: H03K 3/35625 using complementary field-effect transistors
• CPC Class Codes: H03K 5/151 with two complementary outputs
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices

Abstract

Techniques for providing improved memory flip-flops and other logic circuits are described. A flip-flop uses only one p-channel transistor to drive the output node strongly to achieve fast results. To reduce diffusion area, parallel logic is substantially eliminated and only series branches are used, in critical areas. This allows all pull-up transistors and/or all pull-down transistors to be formed from contiguous active areas. The D-to-Q path is reduced, and the clock is used to control the output. The clock becomes the dominant controller of the output when it is located closest to the output. Placing the clock devices closest to the clocked nodes reduces clock skew. The rising D response time and falling D response time are caused to be as close as possible to reduce the overall cycle time. To reduce parasitics in the circuit, complex-gates are used which are asymmetric. Even multiples of series branches per gate are used to share contacts and eliminate breaks in the layout diffusion. Adding complex-gates to a circuit while using asymmetric gates for smaller layouts achieves additional functionality. One component of the clock, along with the master drive circuit, is used to drive the slave latch of a flip-flop to avoid inserting additional gates into the logic of the fast output path. Reset and set circuitry is designed to be outside the critical path of the clock, and outside the slave latch, to provide rapid Q output response time to the clock and D inputs.

Claims

1. A scan flip-flop comprising:

a master latch and a slave latch, the slave latch coupled to receive an output of the master latch and to provide an output of the flip-flop, the master latch including an input sample stack, a scan input stack, and a hold stack,

the input sample stack including a first plurality of transistors having source-to-drain paths coupled in series between a first supply node and a second supply node, wherein two transistors of the first plurality of transistors share a common source-drain node as an output of the master latch, wherein one of said two transistors is controlled by a scan control input for placing the flip-flop into a scan mode, and the other of said two transistors is controlled by a complement of the scan control input, and wherein another two transistors of the first plurality of transistors are controlled by a first data input of the flip-flop,

the scan input stack including a second plurality of transistors having source-to-drain paths coupled in series between the first supply node and the second supply node, wherein two transistors of the second plurality of transistors share a common source-drain node as said output of the master latch, wherein one of said two transistors of the second plurality of transistors is controlled by the scan control input, and the other of said two transistors of the second plurality of transistors is controlled by a complement of the scan control input, and wherein another two transistors of the second plurality of transistors are controlled by a second data input of the flip-flop, and

the hold stack coupled to the output of the master latch.

2. A scan flip-flop comprising:

a slave latch; and

a master latch coupled to the slave latch, the master latch including a first plurality of transistors having source-to-drain paths coupled in series in a path from a first supply node to a second supply node, said path including only said first plurality of transistors, a connection between two of the first plurality of transistors forming an output of the master latch, wherein at least one of the first plurality of transistors is controlled by a scan control input for placing the flip-flop into a scan mode and at least one other of the first plurality of transistors is controlled by a first data input of the flip-flop.

3. A scan flip-flop as recited in claim 2, further comprising a hold stack coupled to the output of the master latch, wherein the master latch further comprises a second plurality of transistors having source-to-drain paths coupled in series between the first supply node and the second supply node, a connection between two of the second plurality of transistors forming the output of the master latch, wherein at least one of the second plurality of transistors is controlled by the scan control input and at least one other of the second plurality of transistors is controlled by a second data input of the flip-flop.

4. A scan flip-flop as recited in claim 3, wherein the first plurality of transistors and the second plurality of transistors are mutually exclusive.

5. A scan flip-flop as recited in claim 4, wherein at least one of the first plurality of transistors and at least one of the second plurality of transistors is controlled by a complement of the scan control input.