Linear power amplifier bias circuit

• US 6,333,677 B1
• Filed: 10/10/2000
• Issued: 12/25/2001
• Est. Priority Date: 10/10/2000
• Status: Expired due to Term

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Dening, David C.
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): Choe, Henry
• Application Number:
  US09/684,825
• Time in Patent Office: 441 Days
• Field of Search: 330/285, 330/296, 330/302
• US Class Current: 330/296
• CPC Class Codes: H03F 1/302 in bipolar transistor amplifiers H03F1/303, H03F1/305, H03F1/307 take precedence
• CPC Class Codes: H03F 1/565 using inductive elements
• CPC Class Codes: H03F 3/19 with semiconductor devices only

Abstract

A bias circuit suitable for use with a radio frequency linear power amplifier compensates for amplifier gain compression by providing bias current responsive to an amplitude of an RF signal to be amplified at a bias current gain greater than unity. The bias circuit comprises a minimal number of active and passive components and is suitable for implementation in a range of process technologies. Bias current gain may be configured over a range of less than to greater than unity gain by adjusting a reference voltage supplied to the bias circuit and by adjusting a resistor value included within the bias circuit. In implementation, the bias circuit is configured to have a bias current gain that complements a characteristic gain compression associated with a particular radio frequency power amplifier.

Claims

1. A bias circuit for biasing a transistor power amplifier, said bias circuit comprising:

a first transistor comprising a base, a collector, and an emitter, said base of said first transistor coupled to a base of an associated amplifier transistor and a first end of an input signal coupling capacitor, and said emitter coupled to a signal ground node common with an emitter of the associated amplifier transistor;

a second transistor comprising a base, a collector, and an emitter, said base of said second transistor coupled to said collector of said first transistor, and said collector of said second transistor coupled to an operating voltage signal; and

a first impedance element having a first end coupled to said collector of said first transistor and said base of said second transistor and a second end coupled to a reference voltage signal;

wherein said bias circuit is operative to provide a bias current responsive to an amplitude of the radio frequency signal to be amplified with a current gain capable of being configured to be greater than unity.

2. The bias circuit of claim 1 wherein said first impedance element comprises a first combination of resistive and reactive elements configured to provide desired DC and AC current gain characteristics for said bias circuit.

3. The bias circuit of claim 1 wherein said first impedance element is one of the group consisting of a first resistor and a first inductor.

4. The bias circuit of claim 1 wherein said first impedance element comprises a first series combination of a first inductor and a first resistor.

5. The bias circuit of claim 1 wherein said first impedance element comprises a first resistor connected in parallel with a first capacitor.

6. The bias circuit of claim 1 further comprising a second impedance element having a first end coupled to said emitter of said second transistor and a second end coupled to said base of said first transistor.

7. The bias circuit of claim 6 wherein said second impedance element comprises a second combination of resistive and reactive elements configured to provide desired DC and AC current gain characteristics for said bias circuit.

8. The bias circuit of claim 6 wherein said second impedance element is one of the group consisting of a second resistor and a second inductor.

9. The bias circuit of claim 6 wherein said second impedance element comprises a second series combination of a second inductor and a second resistor.

10. The bias circuit of claim 6 wherein said second impedance element comprises a second resistor connected in parallel with a second capacitor.

11. The bias circuit of claim 6 wherein an overall impedance value of said first impedance element and an overall impedance value of said second impedance element are adjusted for a given value of the reference voltage signal to configure the current gain of said bias circuit, and further wherein increasing the overall impedance value of said first impedance at a given operating frequency tends to increase the current gain of said bias circuit, while increasing the overall impedance value of said second impedance element at the given operating frequency tends to decrease the current gain of said bias circuit.

12. The bias circuit of claim 1 wherein said bias circuit is configured to have a bias current gain such that said bias current provides an amount of charge to said input signal coupling capacitor during negative-going portions of the radio frequency signal to be amplified sufficient to recharge said input signal coupling capacitor to a voltage proportionate to an input signal amplitude of the radio frequency signal to be amplified over a range of input signal amplitudes.

13. The bias circuit of claim 1 wherein said bias circuit is implemented in an Indium Phosphide semiconductor process technology.

14. The bias circuit of claim 1 wherein said bias circuit is implemented in a Silicon Germanium semiconductor process technology.

15. The bias circuit of claim 1 wherein said bias circuit is fabricated with a desired size ratio between said first transistor and the associated transistor power amplifier.

16. The bias circuit of claim 15 wherein said desired size ratio is such that said first transistor is smaller than the associated transistor power amplifier such that the associated transistor power amplifier receives more base current than said first transistor.

17. The bias circuit of claim 1 wherein a collector voltage of said first transistor has an amplified response to the radio frequency signal to be amplified based on a current gain of said first transistor and an impedance of said first impedance element, and wherein the collector voltage of said first transistor drives said base of said second transistor such that the bias current provided by said bias circuit may be configured with a desired current gain relative to an amplitude of the radio frequency signal to be amplified.

18. The bias circuit of claim 1 wherein said bias circuit is operative such that said first transistor turns off and said second transistor turns on during a negative-going swing of the radio frequency signal to be amplified, and said first transistor turns on and said second transistor turns off when the radio frequency signal to be amplified exceeds a given amplitude during positive-going swings of the radio frequency signal to be amplified.

19. The bias circuit of claim 18 wherein a maximum drive signal appearing on said base of said second transistor develops when said first transistor turns off.

20. A bias circuit for biasing a radio frequency amplifier, said bias circuit comprising:

a first transistor driven by a radio frequency signal to be amplified by the radio frequency amplifier and adapted to output a bias control signal responsive to the radio frequency signal to be amplified; and

a second transistor driven by said bias control signal and adapted to provide a bias current to the radio frequency amplifier responsive to said bias control signal;

wherein said bias circuit provides said bias current to the radio frequency amplifier proportional to an amplitude of the radio frequency signal to be amplified.

21. The bias circuit of claim 20 further comprising:

a first impedance element coupled between a bias voltage supply and said first transistor; and

a second impedance element coupled between said second transistor and the radio frequency power amplifier;

wherein a current gain of said bias current may be adjusted to a desired value based on setting values for said first and second impedance elements.

22. The bias circuit of claim 20 wherein said second transistor derives said bias current from an operating voltage supply.

23. The bias circuit of claim 20 wherein said second transistor derives said bias current from an output of the radio frequency amplifier.

24. A radio frequency power amplifier circuit comprising:

a first transistor having a base, a collector, and an emitter, said emitter of said first transistor coupled to a signal ground node;

a second transistor having a base, a collector, and an emitter, said collector of said second transistor coupled to a voltage source, and said base of said second transistor coupled to said collector of said first transistor;

a third transistor having a base, a collector, and an emitter, said emitter of said third transistor coupled to said signal ground node and said base of said third transistor coupled to said base of said first transistor, said collector of said third transistor providing an amplified output signal;

a first impedance element having a first end coupled to said collector of said first transistor and said base of said second transistor and a second end coupled to a reference voltage signal; and

a first capacitor having a first end coupled to a radio frequency signal to be amplified and a second end coupled to said bases of said first and third transistors;

wherein said first and second transistors and said first impedance element cooperate to form a bias circuit providing a bias current proportional to an amplitude of the radio frequency signal received through said first capacitor to be amplified by said third transistor.

25. The radio frequency power amplifier of claim 24 further comprising a second impedance element having a first end coupled to said emitter of said second transistor and a second end coupled to said bases of said first and third transistors and said second end of said first capacitor, and wherein increasing an impedance of said first impedance element tends to increase a current gain of the bias circuit, and increasing an impedance of said second impedance element tends to decrease the current gain of said bias circuit.

26. The radio frequency power amplifier of claim 25 wherein said first and second impedance elements comprise first and second resistors, respectively.

27. The radio frequency power amplifier of claim 25 wherein said first and second impedance elements each comprise first and second combinations of a series resistor and inductor, respectively.

28. The radio frequency power amplifier of claim 25 wherein said first and second impedance elements each comprise a combination of reactive and resistive components selected to impart desired DC and AC gain characteristics to the current gain of said bias circuit.

29. The radio frequency power amplifier circuit of claim 24 wherein said voltage source coupled to said collector of said second transistor is said amplified output signal taken from said collector of said third transistor.

30. The radio frequency power amplifier circuit of claim 24 further comprising an output matching network having a first connection coupled to said collector of said third transistor, a second connection coupled to a supply voltage signal, and a third connection coupled to an output load and providing a final RF output signal, said output matching network providing a desired load to said collector of said third transistor.

31. The radio frequency power amplifier circuit of claim 30 wherein said collector of said second transistor connects to said collector of said third transistor such that said amplified output signal serves as the supply voltage signal for said second transistor.

32. The radio frequency amplifier circuit of claim 24 wherein said output matching network includes one or more inductive circuit elements such that said amplified output signal increases in voltage when said third transistor turns off during negative-going excursions of the radio frequency signal to be amplified, thereby providing adequate voltage to the collector of said second transistor for generating a bias current used in charging said first capacitor.

33. The radio frequency amplifier circuit of claim 24 wherein said radio frequency amplifier circuit is implemented in an integrated circuit device.

34. An integrated circuit device comprising:

a reference voltage node adapted to receive a reference voltage signal;

an operating voltage node adapted to receive an operating voltage signal;

an output signal node adapted to provide an output RF signal;

an input signal node adapted to receive a radio frequency signal to be amplified;

a plurality of coupling capacitors having first ends commonly connected to said input signal node;

a plurality of parallel amplifier transistors, each having a base, an emitter, and a collector, wherein respective ones of said bases are connected to respective ones of second ends of said coupling capacitors, all said emitters are commonly connected to a signal ground node and all said collectors are commonly connected to said output signal node; and

a plurality of bias circuits wherein respective ones of said bias circuits are connected to respective ones of said parallel amplifier transistors and adapted to provide a bias current that operates said parallel amplifier transistors in a substantially linear mode of operation over a range of amplitudes of the radio frequency signal to be amplified, each said bias circuit comprising;

(i) a first transistor comprising a base, a collector, and an emitter, said base coupled to said base of a respective one of said amplifier transistors and said second end of a respective one of said coupling capacitors, and said emitter coupled to said signal ground node;

(ii) a second transistor comprising a base, a collector, and an emitter, said base coupled to said collector of said first transistor, and said collector coupled to said operating voltage node; and

(iii) a first impedance element having a first end coupled to said collector of said first transistor and said base of said second transistor and a second end coupled to said reference voltage node.

35. The integrated circuit device of claim 34 wherein each said bias circuit further comprises a second impedance element having a first end coupled to said emitter of said second transistor and a second end coupled to said base of said first transistor, said base of said respective amplifier transistor, and said second end of said respective coupling capacitor.

36. The integrated circuit device of claim 34 further comprising an output matching network having first connection coupled to said output signal node, a second connection coupled to an operating voltage signal, and a third node coupled to an output load, wherein a circuit network included in said output matching network connects said output signal node to said output load through a circuit network impedance matched to an impedance of said output load.

37. The integrated circuit device of claim 36 wherein said operating voltage node commonly connecting all said collectors of said second transistors in said plurality of bias circuits connects to said first connection of said output matching network such that said bias circuits receive said amplified output signal on said collectors of said parallel amplifier transistors as a bias circuit operating voltage signal.

38. The integrated circuit device of claim 34 further comprising a reference voltage circuit adapted to provide a reference voltage signal to said reference voltage node.

39. The integrated circuit device of claim 34 further comprising a like plurality of input resistors disposed in series between said second ends of said coupling capacitors and said bases of said parallel amplifier transistors such that respective ones of said amplifier transistors receive the radio frequency signal to be amplified through a series connection to said input signal node comprising a respective one of said coupling capacitors and a respective one of said input resistors.

40. A bias circuit for biasing a transistor power amplifier, said bias circuit comprising:

a first transistor circuit for generating an analog control signal responsive to an amplitude of a radio frequency signal to be amplified by the transistor power amplifier; and

a second transistor circuit for generating a bias current responsive to said analog control signal;

wherein said bias current maintains the transistor power amplifier in a linear mode of amplification across a range of amplitudes of the radio frequency signal to be amplified.

41. The bias circuit of claim 40 wherein a signal gain of said first transistor circuit determines a relative relationship between the radio frequency signal to be amplified and the analog control signal, and wherein the signal gain of said first transistor circuit may be configured as desired such that said second transistor circuit provides a bias current with a desired bias current gain.