Source driver of liquid crystal display and method for driving the same

• US 6,333,730 B1
• Filed: 02/13/1998
• Issued: 12/25/2001
• Est. Priority Date: 03/05/1997
• Status: Expired due to Term

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Electronics, Inc. (LG Corporation)
• Inventors: Lee, Seung-Jong
• Primary Examiner(s): Hjerpe, Richard
• Assistant Examiner(s): NGUYEN, FRANCIS N
• Application Number:
  US09/023,713
• Time in Patent Office: 1,411 Days
• Field of Search: 345/100, 345/98, 345/99, 345/213, 345/507, 345/132, 345/88, 345/204, 345/197, 348/511
• US Class Current: 345/100
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2310/0283 Arrangement of drivers for different directions of scanning
• CPC Class Codes: G09G 2310/0297 Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• CPC Class Codes: G09G 2340/0414 Vertical resolution change
• CPC Class Codes: G09G 3/3685 Details of drivers for data electrodes
• CPC Class Codes: G09G 3/3688 suitable for active matrices only

Abstract

A source driver of a liquid crystal display (LCD) having a multi-scan function and a method for driving the same are disclosed, the source drive of an LCD includes a shift register for shifting and outputting a carry input/output (I/O) signal, a latch section including first, second, and third latches for sequentially storing R, G, and B external image signal data, holding the stored data, and outputting stored image signal data synchronously with the carry I/O signal. Further, a digital/analog (D/A) converter for converts the image data output by the latch section into an analog image signal based on external POL signal, a data output part for outputs the analog image signal, and a controlling section controls operation of the three latches so as not to operate data input and data output in the same latch.

Claims

1. A liquid crystal device (LCD) source driver comprising:

a shift register for shifting and outputting a carry input/output (I/O) signal,

a latch section including first, second and third latches, each for inputting, R, G and B external image data, holding the input date, or and outputting the held data synchronously with the carry I/O signal;

a digital/analog (D/A) converter for converting the image data output by the latch section into an analog image signal synchronously with an external polarity control signal;

a data output section for outputting the analog signal to an LCD panel; and

a controlling section for controlling operation of the first, second and third latches so as to operate one of the first, second and third latches in input mode, another of the latches in hold mode and the other of the latches in output mode.

2. The LCD source driver as claimed in claim 1, wherein said controling section comprises:

a first selecting section for outputting a signal to select one of the first, second, and third latches to be operated in a data latch mode;

a phase lock loop (PLL) section for outputting a dot clock by dividing a horizontal synchronizing signal of an input image signal into a number of lines of a corresponding LCD module;

a variable oscillating section for outputting gate start pulses of the number of scan lines of the LCD module for a vertical synchronizing period;

a comparing section for ensuring operating in a data output mode and data latch mode occur in separate latches of the latch section; and

a second selecting section for selecting one of the latches to be operated in data output mode according to a signal output by the comparing section.

3. The LCD source driver as claimed in claim 2, wherein said first selecting section further comprises a rotator for repeatedly outputting a selecting signal by using a horizontal synchronizing signal of input image signal as a clock signal and a vertical synchronizing signal as a clear and load signal, so that the first, second, and then third latches are sequentially selected in latch mode.

4. The LCD source driver as claimed in claim 2, wherein said second selecting section further comprises a rotator for repeatedly selecting a selecting signal by using an output signal of the comparing section as a clock signal and a vertical synchronizing signal of input image data as a clear and load signal, so that the third, first, and then second latches are selected sequentially in data output mode.

5. The LCD source driver as claimed in claim 2, wherein the comparing section further comprises:

a first NAND gate for performing an inverted logical product of a first latch mode selecting signal output by the first selecting section and a third output mode selecting signal output by the second selecting section;

a second NAND gate for performing an inverted logical product of a second latch mode selecting signal output by the first selecting section and a first output mode selecting signal output by the second selecting section;

a third NAND gate for performing an inverted logical product of a third latch mode selecting signal output by the first selecting section and a second output mode selecting signal output by the second selecting section;

a first AND gate for performing a logical product of the signals output by the first, second, and third NAND gates; and

a second AND gate for operating a logical product of an output signal of the first AND gate and an output signal of the variable oscillating section and outputting the logical result to the second selecting section.

6. An liquid crystal device (LCD) source driver comprising:

first, second, and third memory sections for storing a line signal of image data by an external control;

an output selecting section for selecting an output signal of one of the first, second, and third memory sections; and

a controlling section for controlling the writing and reading of each of the first, second, and third memory sections and the output signal of the output selecting section so as to operate one of the first, second, and third memory sections in input mode, another of the memory sections in hold mode, and the other of the memory sections in output mode.

7. The LCD source driver as claimed in claim 6, wherein the output selecting section comprises tri-state buffers for buffering data output by each of the first, second, and third memory sections.

8. The LCD source driver as claimed in claim 6, wherein the first, second, and third memory sections comprise:

a multiplexer for outputting either a reading clock or a writing clock according to a control signal for the controlling section;

an OR gate for performing a logical product of input/output selecting signals of a corresponding memory and an inverter for inverting an input selecting signal of the controlling section; and

a memory for reading or writing according to the controlling section by inputting a selecting signal of the controlling section through the inverter, by using an output of the multiplexer as an address clock and an output of the OR gate as an address clear signal.

9. The LCD source driver as claimed in claim 6, wherein the controlling section comprises:

a first selecting section for outputting a first set of selecting signals so as to operating one for the first, second and third memory sections in an input mode;

a phase lock loop section for outputting a dot clock by dividing a horizontal signal of an input image signal into the number of lines of a corresponding LCD module;

a variable oscillating section for outputting gate start pulses of the number of scan lines of the LCD module for a vertical synchronizing period;

a vertical synchronizing signal counter for outputting vertical synchronizing signals of the LCD panel by counting clock signals output by the variable oscillating part, of as many as the number of the lines of the corresponding LCD module;

a comparing section for performing a comparison operation so that one of the memory sections does not operate simultaneously in input mode and output mode; and

a second selecting section for outputting a second set of selecting signals so as to operate one of the first, second and third memory sections in output mode.

10. The LCD source driver as claimed in claim 9, wherein the first selecting section comprises:

a ternary counter for counting in ternary by using a vertical synchronizing signal of an input image signal as a reset signal and a horizontal synchronizing signal as a clock signal; and

a decoder for outputting first, second and third selecting input signals so as to operate one of the three memory sections in input mode by decoding a signal output by the ternary counter.

11. The LCD source driver as claimed in claim 9, wherein the first selecting section outputs a selecting signal so as to sequentially operate the first, second, and third memory sections in an input mode.

12. The LCD source driver as claimed in claim 9, wherein the second selecting section comprises:

a ternary counter for counting in ternary by using a vertical synchronizing signal of input image data as a reset signal and in output signal of the comparing part as a clock signal; and

a decoder for outputting first, second and third selecting output signals so as to operate one of the three memory sections in output mode by decoding a signal output by the ternary counter.

13. The LCD source driver as claimed in claim 9, wherein the second selecting section outputs a selecting signal so as to sequentially operate the third, first, and then second memory sections in output mode.

14. The LCD source driver as claimed in claim 9, wherein the comparing section comprises:

a first AND gate for performing a logical product of a first memory section first selecting output signal of the second selecting section and a second memory section second selecting input signal of the first selecting section;

a second AND gate for performing a logical product of a second memory section second selecting output signal of the second selecting section and a third memory third selecting input signal of the first selecting section;

a third AND gate for performing a logical product of a third memory section third selecting output signal of the second selecting section and a first memory first selecting input signal of the first selecting section;

a NOR gate for performing a logical product of output signals of the first, second, and third AND gates for inversion; and

a fourth AND gate for performing a logical product of an output of the NOR gate and an output of the vertical synchronizing signal counter and outputting the logical product.

15. A method for driving an LCD source driver including first, second, and third memories for displaying image signals of different resolutions, comprising the steps of:

repeatedly and sequentially selecting the first, second, and third memories in an input mode, and then simultaneously and repeatedly selecting the third, first, and second memories in output mode;

selecting a memory previously selected in output mode when a memory which is being operated in input mode is selected in output mode due to differences between input and output rates corresponding to image signals of different resolutions; and

repeating the first and second steps for a vertical synchronizing period of an input image signal.

16. A liquid crystal device (LCD) source driver comprising:

a shift register for shifting and outputting a carry input/output (I/O) signal;

a latch section including first, second and third latches for sequentially storing external image data (R, G and B), holding the stored data, and outputting the stored data synchronously with the carry I/O signal;

a digital/analog (D/A) converter for converting the image data output by the latch section into an analog image signal synchronously with an external polarity control (POL) signal;

a data output section for outputting the analog image signal to an LCD panel;

a controlling section for controlling operation of the first, second, and third latches so as to operate one of the first, second and third latches in data input mode, another of the latches in data hold mode and the other of the latches in data output mode wherein the controlling section comprises;

a first selecting section for outputting a signal to select one of the first, second, and third latches to be operated in a data latch mode;

a phase lock loop (PLL) section for outputting a dot clock by dividing a horizontal synchronizing signal of an input image signal into a number of lines of a corresponding LCD module;

a variable oscillating section for outputting gate start pulses of the number of scan lines of the LCD module for a vertical synchronizing period;

a comparing section so as to operate one of the first, second and third latches in data output mode, and another of the latches in data latch mode; and

a second selecting section for selecting one of the latches to be operated in data output mode according to a signal output by the comparing section.

17. The LCD source driver as claimed in claim 16, wherein said first selecting section further comprises a rotator for repeatedly outputting a selecting signal by using a horizontal synchronizing signal of input image signal as a clock signal and a vertical synchronizing signal as a clear and load signal, so that the first, second, and then third latches are sequentially selected in latch mode.

18. The LCD source driver as claimed in claim 16, wherein said second selecting section further comprises a rotator for repeatedly selecting a selecting signal by using an output signal of the comparing section as a clock signal and a vertical synchronizing signal of input image data as a clear and load signal, so that the third, first, and then second latches are selected sequentially in data output mode.

19. The LCD source driver as claimed in claim 18, wherein the comparing section further comprises:

a first NAND gate for performing an inverted logical product of a first latch mode selecting signal output by the first selecting section and a third output mode selecting signal output by the second selecting section;

a second NAND gate for performing an inverted logical product of a second latch mode selecting signal output by the first selecting section and a first output mode selecting signal output by the second selecting section;

a third NAND gate for performing an inverted logical product of a third latch mode selecting signal output by the first selecting section and a second output mode selecting signal output by the second selecting section;

a first AND gate for performing a logical product of the signals output by the first, second, and third NAND gates; and

a second AND gate for operating a logical product of an output signal of the first AND gate and an output signal of the variable oscillating section and outputting the logical result to the second selecting section.