Data processor having unified memory architecture providing priority memory access

• US 6,333,745 B1
• Filed: 09/29/1997
• Issued: 12/25/2001
• Est. Priority Date: 09/30/1996
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Matsuo, Shigeru, Inuzuka, Tatsuki, Nakatsuka, Yasuhiro, Shimomura, Tetsuya, Katsura, Koyo
• Primary Examiner(s): Chauhan, Ulka J.
• Application Number:
  US08/942,689
• Time in Patent Office: 1,548 Days
• Field of Search: 345/501-504, 345/520, 345/521, 345/507, 345/509, 345/515, 345/516, 345/512, 345/202, 345/203, 711/1, 711/6, 711/147, 711/150, 711/151, 711/153, 711/169, 711/173, 395/287, 395/290-294, 395/309, 395/310, 395/856, 395/859, 395/860, 395/868, 395/872, 395/728, 395/732, 395/736
• US Class Current: 345/535
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 2360/128 Frame memory using a Synchronous Dynamic RAM [SDRAM]
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/02 characterised by the way in which colour is displayed details of colour display specific for CRTs G09G1/28; specific for flat matrix panels other than liquid crystal displays G09G3/2003; specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence

Abstract

In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory is generated from the CPU, the memory controller holds it once, requests the display controller to stop the access to the memory which is in execution, when data to the access executed already is transferred from the memory, holds it, and transfers the access request from the CPU bus which is held by the memory. When the access from the CPU bus ends, the memory controller restarts the access stopped in the display controller and passes the held data to the display controller.

Claims

1. A data processor comprising:

a CPU;

a main memory including a portion of said main memory that is used as a frame buffer for storing display data; and

a display controller for controlling display of display data on a display unit using the display data stored in said frame buffer;

a memory controller connected to said main memory via a memory bus, said CPU via a CPU bus, and said display controller via a local bus, for relaying a memory access sequence of said CPU to said main memory between said CPU bus and said memory bus, and for relaying a memory access sequence of said display controller to said main memory between said local bus and said memory bus;

said memory controller, in order to provide priority to the memory access sequence of said CPU every time, including means for suspending execution of the memory access sequence of said display controller to said main memory, when the memory access sequence of said CPU to said main memory starts on said CPU bus during relaying of the memory access sequence of said display controller to said memory bus;

said memory controller including means for resuming the execution of the memory access sequence of said display controller to said main memory after the memory access sequence of the CPU to said main memory ends, and for executing the unexecuted portion of said memory access sequence; and

said memory controller including a buffer for storing data output from said main memory onto said memory bus for the memory access sequence of said display controller to said main memory when execution is suspended, and then outputting the data stored in said buffer to said display controller when the memory access sequence of said display controller is resumed, wherein a difference between a throughput of said memory bus and a throughput of said CPU bus is greater than a reading rate of said display controller for reading data from said main memory.

2. A data processor of claim 1, wherein said main memory is a memory accessed by a page mode access sequence, and said buffer of the memory controller stores a row address included in the memory access sequence of said display controller relayed to said memory bus, and outputs the stored row address to said main memory via said memory bus before resuming execution of the memory access sequence of said display controller.

3. A processor comprising:

a CPU;

a main memory including a portion of said main memory that is used as a frame buffer for storing display data; and

a display controller for controlling display of display data on a display unit using the display data stored in said frame buffer;

a memory controller connected to said main memory via a memory bus, said CPU via a CPU bus, and said display controller via a local bus, for relaying a memory access sequence of said CPU to said main memory between said CPU bus and said memory bus, and for relaying a memory access sequence of said display controller to said main memory between said local bus and said memory bus;

said memory controller including means for suspending execution of the memory access sequence of said display controller to said main memory when the memory access sequence of said CPU to said main memory starts on said CPU bus during relaying of said memory access sequence of said display controller to said memory bus;

said memory controller including means for resuming the execution of the memory access sequence of said display controller to said main memory after the memory access sequence of said CPU to said main memory ends, and for executing the unexecuted portion of the memory access sequence;

said memory controller including address storage means for storing an address range of said main memory data in which address ranges are stored in said main memory after compression;

said memory controller including compression means for compressing the data;

said memory controller including recovery means for recovering the compressed data;

said memory controller including means for relaying a memory access sequence for writing, when the memory access sequence of said CPU on said CPU bus to said main memory is a memory access sequence for writing data within the address range registered in said address storage means of the data being compressed by said compression means into said main memory;

said memory controller including means for relaying a memory access sequence for reading, when said memory access sequence of said display controller on said local bus to said main memory is a memory access sequence for reading data from the address range registered in said address storage means of the compressed data stored in said main memory to said memory bus, and further relaying recovered data by said recovery means of the read data from said main memory to said local bus; and

wherein the address range of the main memory data in which are stored after compression is used as a frame buffer and the compression is a compression for selecting two data among three or more data corresponding to three or more pixels as first data and second data and converting the three or more data to said first data, data indicating the difference value between the first data and the second data, and data indicating which of the three or more data is closer to the first data or the second data.

4. A main controller IC chip for controlling access of a main memory of a CPU comprising:

a display controller using a part of a main memory as a frame buffer for storing display data and controlling display of display data;

a memory controller connected to said main memory via a memory bus, to said CPU via a CPU bus, and to said display controller via a local bus, for providing priority memory access to said CPU by relaying a memory access sequence of said CPU to said main memory between said CPU bus and said memory bus, and relaying a memory access sequence of said display controller to said main memory between said local bus and said memory bus;

said memory controller including;

a control circuit for suspending execution of the memory access sequence of said display controller to said main memory when the memory access sequence of said CPU to said main memory starts on said CPU bus during relaying of the memory access sequence of said display controller to said memory bus, for resuming the execution of the memory access sequence of said display controller to said main memory after the memory access sequence of said CPU to said main memory is completed, including executing the unexecuted portion of the memory access sequence; and

a buffer for storing a memory access request from said display controller while the execution of the memory access sequence of said display controller is suspended, the stored accessed request being used to resume execution of the memory access sequence of said display controller, wherein a difference between a throughput of said memory bus and a throughput of said CPU bus is greater than a reading rate of said display controller for reading data from said main memory.

5. A data processing system comprising:

a CPU;

a memory for storing programs and display data;

a memory controller connected to said CPU via a CPU bus and said memory via a memory bus, for providing priority to an access request from said CPU to said memory, said memory controller having a display controller for reading the display data stored in said memory, and a buffer for storing an access request from said display controller to said memory, and execution of the memory access by said display controller in response to an access request from said CPU; and

wherein said display controller resumes execution of the memory access based on the access request stored in said buffer after completion of the memory access from said CPU, and wherein a difference between a throughput of said memory bus and a throughput of said CPU bus is greater than a reading rate of said display controller for reading data from said memory.

6. The data processing system of claim 5, wherein the access request of said display controller stored in said buffer comprises a read request.

7. The data processing system of claim 6, wherein the read request comprises a read command and an address.

8. The data processing system of claim 7, wherein the read request further comprises data read from the memory.

9. The data processing system of claim 5, wherein the access request of said display controller stored in said buffer comprises a write request.

10. The data processing system of claim 9, wherein the write request comprises a write command and an address.

11. A data processing system comprising:

a CPU;

a memory for storing programs and display data;

a memory controller connected to said CPU via a CPU bus and to said memory via a memory bus, for providing priority to an access request from said CPU to said memory, said memory controller including a drawing circuit for producing the display data to be stored in said memory, and a buffer for storing an access request from said drawing circuit to said memory and suspending execution of a memory access by said drawing circuit in response to an access request from said CPU; and

wherein said drawing circuit resumes execution of the memory access based on the access request stored in said buffer after completion of the memory access from said CPU, and wherein a difference between a throughput of said memory bus and a throughput of said CPU bus is greater than a reading rate of said drawing circuit for reading data from said memory.

12. The data processing system of claim 11, wherein the access request of said drawing circuit stored in said buffer comprises a read request.

13. The data processing system of claim 11, wherein the access request of said drawing circuit stored in said buffer comprises a write request.