Delay locked loop for use in synchronous dynamic random access memory

• US 6,333,896 B1
• Filed: 10/31/2000
• Issued: 12/25/2001
• Est. Priority Date: 11/01/1999
• Status: Expired due to Term

• Current Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Lee, Seong-Hoon
• Primary Examiner(s): Dinh, Son T.
• Application Number:
  US09/703,405
• Time in Patent Office: 420 Days
• Field of Search: 365/233, 365/194, 365/189.07, 327/158, 327/159, 327/160, 327/161
• US Class Current: 365/233.1
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator

Abstract

A delay locked loop (DLL) for compensating for a skew in a synchronous dynamic random access memory includes: a delay model means for delaying an external clock signal by the skew to generate a delayed clock signal; a control unit, in response to the external clock signal and the delayed clock signal, for generating control signals, wherein the control signal includes a control clock signal, a delayed control signal, a replication signal and a replication enable signal; a first voltage control oscillator, in response to the control clock signal and the delayed control signal, for generating a measurement oscillating signal; a second voltage controlled oscillator, in response to the replication signal and the replication enable signal, for generating a replication oscillating signal; a first unit, in response to the measurement oscillating signal and the replication oscillating signal, for generating a DLL clock signal; and a second unit for comparing a phase difference between the DLL clock signal and the external clock signal to generate a voltage control signal, wherein time periods of the measurement oscillating signal and the replication oscillating signal are changed by the voltage control signal.

Claims

1. A delay locked loop (DLL) for compensating for a skew in a synchronous dynamic random access memory, comprising:

a delay model means for delaying an external clock signal by the skew to generate a delayed clock signal;

a control means, in response to the external clock signal and the delayed clock signal, for generating control signals, wherein the control signal includes a control clock signal, a delayed control signal, a replication signal and a replication enable signal;

a first voltage controlled oscillation means, in response to the control clock signal and the delayed control signal, for generating a measurement oscillating signal;

a second voltage controlled oscillation means, in response to the replication signal and the replication enable signal, for generating a replication oscillating signal;

a first means, in response to the measurement oscillating signal and the replication oscillating signal, for generating a DLL clock signal; and

a second means for comparing a phase difference between the DLL clock signal and the external clock signal to generate a voltage control signal, wherein time periods of the measurement oscillating signal and the replication oscillating signal are changed by the voltage control signal.

2. The delay locked loop as recited in claim 1, wherein the control clock signal is enabled to a high level from a first rising edge to a second rising edge of the external clock signal.

3. The delay locked loop as recited in claim 2, wherein the delayed control signal is enabled to a low level from a first rising edge to a second rising edge of the delayed clock signal.

4. The delay locked loop as recited in claim 3, wherein the measurement oscillating signal is toggled while both the control clock signal and the delayed control signal are enabled.

5. The delay locked loop as recited in claim 4, wherein the first voltage controlled oscillation means includes:

a NOR gate having an input terminal receiving the delayed control signal;

a delay control unit for delaying an output signal of the NOR gate in response to the voltage control signal;

a NAND gate for NANDing the control clock signal and an output signal of the delay control unit;

a delay unit for delaying an output signal of the NAND gate, wherein an output signal of the delay unit is feedback to another input terminal of the NOR gate; and

an inverter for inverting the output signal of the NAND gate to generate the measurement oscillating signal.

6. The delay locked loop as recited in claim 4, wherein the second voltage controlled oscillation means includes:

a NOR gate having an input terminal receiving the replication signal;

a delay control unit for delaying an output signal of the NOR gate in response to the voltage control signal;

a NAND gate for NANDing the replication enable signal and an output signal of the delay control unit;

a delay unit for delaying an output signal of the NAND gate, wherein an output signal of the delay unit is feedback to another input terminal of the NOR gate; and

an inverter for inverting the output signal of the NAND gate to generate the replication oscillating signal.

7. The delay locked loop as recited in claim 4, wherein the first means includes:

a plurality of delay units for shifting a low level of the delayed control signal to corresponding nodes in response to the measurement oscillating signal;

a plurality of registers for storing shifted low levels on the nodes; and

a delay replication unit, in response to an output signal of the registers, for shifting the replication signal according to the replication oscillating signal to generate the DLL clock signal.

8. The delay locked loop as recited in claim 7, wherein each register includes:

a first inverter for receiving a voltage level of corresponding node to output an inverted signal;

a transmission gate for transmitting the inverted signal in response to the control clock signal;

a storage unit for storing the an output signal of the transmission gate; and

a second inverter for inverting an output signal of the storage unit.

9. The delay locked loop as recited in claim 1, wherein the second means includes:

a second delay mode for delaying the DLL clock signal by the skew to generate a comparison clock signal;

a phase detector for comparing the phase difference to generate an up pulse signal and a down pulse signal according to the phase difference;

a charge pump for decreasing and increasing the voltage level of the voltage control signal in response to the up pulse signal and the down pulse signal; and

a filter for removing high-frequency noise of the voltage control signal.

10. The delay locked loop as recited in claim 9, wherein the down pulse signal is generated if the comparison clock signal precedes the external clock signal, thereby decreasing the voltage level of the voltage control signal.