System for the manipulation of secure data
First Claim
1. A system for the manipulation of secure data having electronics or software, or both, that are designed to operate within a specific clock speed range;
- the system being provided with a clock frequency limiter in the clock signal line, upstream of elements that are to be protected, where the limiter involves an enable gate having an input port, an output port and a control port, and is located in the clock signal line to pass the clock signal from the input port to the output port only when it is enabled by a signal at the control port;
clock signal taps are connected to pass clock signals from upstream and downstream of the enable gate to an edge detector, and the output of the edge detector is passed through a delay to the control port of the enable gate.
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Accused Products
Abstract
This invention concerns a system for the manipulation of secure data which includes electronics or software, or both, that are designed to operate within a specific clock speed range. The system is provided with a clock frequency limiter in the clock signal line, upstream of elements that are to be protected. The limiter involves an enable gate having an input port, an output port and a control port, and is located in the clock signal line to pass the clock signal from the input port to the output port only when it is enabled by a signal at the control port. Clock signal taps are connected to pass clock signals from upstream and downstream of the enable gate to an edge detector, and the output of the edge detector is passed through a delay to the control port of the enable gate.
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Citations
6 Claims
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1. A system for the manipulation of secure data having electronics or software, or both, that are designed to operate within a specific clock speed range;
- the system being provided with a clock frequency limiter in the clock signal line, upstream of elements that are to be protected, where the limiter involves an enable gate having an input port, an output port and a control port, and is located in the clock signal line to pass the clock signal from the input port to the output port only when it is enabled by a signal at the control port;
clock signal taps are connected to pass clock signals from upstream and downstream of the enable gate to an edge detector, and the output of the edge detector is passed through a delay to the control port of the enable gate. - View Dependent Claims (2, 3, 4, 5, 6)
- the system being provided with a clock frequency limiter in the clock signal line, upstream of elements that are to be protected, where the limiter involves an enable gate having an input port, an output port and a control port, and is located in the clock signal line to pass the clock signal from the input port to the output port only when it is enabled by a signal at the control port;
Specification