Method for fabricating a simplified CMOS polysilicon thin film transistor and resulting structure

• US 6,335,230 B1
• Filed: 01/04/2000
• Issued: 01/01/2002
• Est. Priority Date: 07/28/1997
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Akram, Salman
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): GURLEY, LYNNE ANN
• Application Number:
  US09/477,203
• Time in Patent Office: 728 Days
• Field of Search: 438/154, 438/149, 438/151, 438/197, 438/353, 438/355, 438/405, 438/412
• US Class Current: 438/149
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: Y10S 257/928 with shorted PN or schottky junction other than emitter junction

Abstract

A method of forming a MOS device using doped and activated n-type and p-type polysilicon layers wherein a first doped and activated polysilicon layer (either n-type and p-type) is patterned on a substrate. An isolation material layer is formed abutting the first doped and activated polysilicon layer in the corners formed at the junction between the first doped and activated polysilicon layer and the substrate. A second doped and activated polysilicon layer (either n-type or p-type) is applied over the first doped and activated polysilicon layer and the isolation material layer. The second doped and activated polysilicon layer is planarized to the height of the first doped and activated polysilicon layer. The first and second doped and activated polysilicon layers are etched to substantially bifurcate the first and second doped and activated polysilicon layers. Further processing steps known in the art are utilized to complete the MOS device. The method of the present invention eliminates ion implantation and annealing steps used in present methods.

Claims

1. A method for forming an activated area for a MOS structure, comprising:

providing a semiconductor substrate with an active surface;

forming a first layer comprising doped polysilicon of a first conductivity type over said active surface;

patterning said first layer to form a first polysilicon area;

forming an isolation barrier laterally adjacent said first polysilicon area and abutting said first polysilicon area in a corner formed at a junction between said first polysilicon area and a surface of a layer or structure upon which said first polysilicon area is located; and

forming a second layer comprising doped polysilicon of a second conductivity type laterally adjacent said isolation barrier.

2. The method of claim 1, further comprising forming a layer comprising an oxide over said active surface.

3. The method of claim 2, wherein said forming said layer comprising said oxide is effected before said forming said first layer comprising doped polysilicon, said patterning said first layer, said forming said isolation barrier, and said forming said second layer comprising doped polysilicon.

4. The method of claim 1, wherein said patterning said first layer comprises:

disposing a mask on said first layer;

etching said first layer through said mask to form said first polysilicon area; and

removing said mask.

5. The method of claim 1, wherein said forming said isolation barrier comprises:

applying a layer comprising isolation material over said semiconductor substrate and said first polysilicon area; and

removing regions of said layer comprising isolation material such that a portion of said layer remains at least in said corner at said junctions between said surface of said layer or structure upon which said first polysilicon area is located and said first polysilicon area.

6. The method of claim 1, wherein said patterning said first layer and said forming said isolation barrier comprise:

forming a layer comprising silicon oxide over said first layer;

forming a layer comprising silicon nitride over said layer comprising silicon oxide;

disposing a mask on said layer comprising silicon nitride;

removing portions of said layer comprising silicon nitride, said layer comprising silicon oxide, and said first layer through at least one of said mask and an overlying layer to form said first polysilicon area;

removing said mask;

removing said layer comprising silicon nitride; and

forming a layer comprising isolation material over at least exposed, lateral edges of said first layer comprising doped polysilicon, said isolation material in a portion of said layer abutting a corner at a junction between said first polysilicon area and a surface of a layer or structure upon which said first polysilicon area is located forming said isolation barrier.

7. The method of claim 1, further comprising:

planarizing said second layer to form a second polysilicon area laterally adjacent said isolation barrier.

8. The method of claim 1, wherein said forming said first layer comprising polysilicon comprises forming said first layer comprising polysilicon to have a p-type conductivity.

9. The method of claim 1, wherein said forming said first layer comprising polysilicon comprises forming said first layer comprising polysilicon to have an n-type conductivity.

10. The method of claim 1, wherein said forming said second layer comprises forming said second layer with at least polysilicon having a p-type conductivity.

11. The method of claim 1, wherein said forming said second layer comprises forming said second layer with at least polysilicon having an n-type conductivity.

12. A method for fabricating activated areas of a MOS structure, comprising:

forming at least one first layer comprising doped polysilicon of a first conductivity type on a surface of a layer or structure on a substrate;

patterning said at least one first layer to form a first polysilicon area;

forming at least one isolation barrier laterally adjacent said at least one first layer comprising doped polysilicon; and

forming at least one second layer comprising doped polysilicon of a second conductivity type laterally adjacent said at least one isolation barrier, opposite said at least one first layer comprising polysilicon.

13. The method of claim 12, further comprising patterning said at least one second layer to form at least one second polysilicon area that is electrically isolated from said one first polysilicon area.

14. The method of claim 12, wherein said patterning said at least one first layer comprises:

disposing a mask on said at least one first layer; and

removing regions of said at least one first layer through said mask.

15. The method of claim 12, wherein said forming said at least one isolation barrier comprises:

applying an isolation material layer over said substrate active surface and said at least one first polysilicon area; and

removing regions of said isolation material layer such that a portion of said isolation material layer remains laterally adjacent said at least one first polysilicon area.

16. The method of claim 12, wherein said patterning said at least one first layer comprising doped polysilicon and said forming said at least one isolation barrier comprise:

applying an oxide layer over said at least one first layer;

applying a nitride layer over said oxide layer;

disposing a mask on said nitride layer;

etching portions of said nitride layer, said oxide layer, and said at least one first layer through at least one of said mask and an overlying layer to form said at least one first polysilicon area;

removing said mask;

removing said nitride layer; and

forming an isolation material layer over at least exposed, lateral edges of said first polysilicon area, at least a portion of said isolation material layer forming said at least one isolation barrier.

17. The method of claim 13, further comprising:

forming at least one mask so as to shield said at least one isolation barrier and portions of said first polysilicon area and said at least one second polysilicon area that are laterally adjacent thereto; and

substantially simultaneously etching said first polysilicon area and said at least one second polysilicon area through said at least one mask.

18. The method of claim 12, wherein said forming said at least one first layer comprises forming said at least one first layer with polysilicon having a p-type conductivity.

19. The method of claim 12, wherein said forming said at least one first layer comprises forming said at least one first layer with polysilicon having an n-type conductivity.

20. The method of claim 12, wherein said forming said at least one second layer comprises forming said at least one second layer with polysilicon having a p-type conductivity.

21. The method of claim 12, wherein said forming said at least one second layer comprises forming said at least one second layer with polysilicon having an n-type conductivity.

22. The method of claim 17, further comprising removing said at least one mask.

23. The method of claim 17, further comprising fabricating at least one gate comprising semiconductive material over said first polysilicon area, said at least one second polysilicon area, and said at least one isolation barrier.

24. The method of claim 23, further comprising disposing a passivation layer over said at least one gate.