Tungsten silicide deposition process

• US 6,335,280 B1
• Filed: 01/13/1997
• Issued: 01/01/2002
• Est. Priority Date: 01/13/1997
• Status: Expired due to Fees

• Current Assignee: ASM America Incorporated (ASM International NV)
• Original Assignee: ASM America Incorporated (ASM International NV)
• Inventors: van der Jeugd, Cornelius Alexander
• Primary Examiner(s): Everhart, Caridad
• Application Number:
  US08/783,815
• Time in Patent Office: 1,814 Days
• Field of Search: 438/586, 438/674, 438/680, 438/935, 438/669, 438/657, 438/737, 438/742
• US Class Current: 438/674
• CPC Class Codes: H01L 21/28052 the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer formed by metal ion implantation H01L21/28044
• CPC Class Codes: H01L 21/28061 the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction H01L21/28052 takes precedence
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/28562 Selective deposition

Abstract

A method of forming a gate metallization in a semiconductor integrated circuit by forming a polycrystalline silicon layer over a gate dielectric layer and then converting the polycrystalline silicon layer into tungsten or tungsten silicide by exposing the polycrystalline silicon to tungsten hexafluoride gas. The method enables the formation of polycrystalline silicon and tungsten or tungsten silicide in the same process cycle in the same reactor or in two similarly configured reactors or in two similarly configured clustered reactors.

Claims

1. A method of forming a gate electrode in a semiconductor integrated circuit device, comprising the steps of:

forming a silicon layer over a gate dielectric layer on a substrate;

forming a tungsten layer by replacing silicon atoms in the silicon layer with tungsten atoms by a displacement reaction prior to patterning the gate electrode; and

annealing said substrate so as to react a substantial portion of said tungsten layer with underlying silicon to form a tungsten silicide layer.

2. The method of claim 1, further comprising the step of removing selected portions of said silicon layer, said tungsten layer and said tungsten silicide layer after annealing said substrate so as to form the gate electrode.

3. The method of claim 1, wherein the step of forming a silicon layer comprises exposing the substrate to a selected flowrate of silane gas at a selected temperature and at a selected pressure.

4. The method of claim 1, wherein the step of forming a silicon layer comprises exposing the substrate to selected flowrates of silane gas and a dopant gas at a selected temperature and at a selected pressure so as to form a doped silicon layer.

5. The method of claim 1, wherein the step of forming a silicon layer comprises exposing the substrate to a selected flowrate of disilane gas at a selected temperature and at a selected pressure.

6. The method of claim 1, wherein the step of forming a silicon layer comprises exposing the substrate to selected flowrates of disilane gas and a dopant gas at a selected temperature and at a selected pressure so as to form a doped silicon layer.

7. The method of claim 1, wherein said silicon layer comprises polycrystalline silicon.

8. The method of claim 1, wherein said silicon layer comprises amorphous silicon.

9. The method of claim 1, wherein the step of forming a tungsten layer comprises exposing said silicon layer to a selected flowrate of tungsten hexafluoride gas at a temperature and a pressure selected to effect the displacement reaction.

10. The method of claim 9, wherein the step of forming a tungsten layer forms a tungsten layer of a selected self-limiting thickness.

11. The method of claim 1, wherein said portion of said silicon layer comprises the entire silicon layer.

12. The method of claim 1, wherein the step of annealing said substrate comprises heating said substrate at a selected temperature in an inert atmosphere.

13. The method of claim 1, wherein the steps of forming a silicon layer, forming a tungsten layer and annealing said substrate occur in the same reactor.

14. The method of claim 1, wherein the steps of forming a silicon layer, forming a tungsten layer and annealing said substrate occur in a plurality of reactors of substantially similar configuration.

15. The method of claim 14, wherein said plurality of reactors comprise a cluster tool.

16. The method of claim 1, wherein said substantial portion of said tungsten layer comprises the entire tungsten layer.

17. A method of forming a gate electrode in a semiconductor integrated circuit device, comprising the steps of:

forming a silicon layer over a gate dielectric layer on a substrate;

forming a tungsten silicide layer by replacing silicon atoms in the silicon layer with tungsten and silicon atoms by a displacement reaction prior to patterning the gate electrode, and

patterning said silicon and tungsten silicide layers to form the gate electrode.

18. The method of claim 17, wherein patterning comprises a photolithographic and etch process.

19. The method of claim 17, further comprising the step of annealing substrate so as to reduce the resistivity of said tungsten silicide layer.

20. The method of claim 19, further comprising the step of removing selected portions of said silicon layer and said tungsten silicide layer so as to form the gate.

21. The method of claim 17, wherein the step of forming a silicon layer comprises exposing the substrate to a selected flowrate of silane gas at a selected temperature and at a selected pressure.

22. The method of claim 17, wherein the step of forming a silicon layer comprises exposing the substrate to selected flowrates of silane gas and a dopant gas at a selected temperature and at a selected pressure so as to form a doped silicon layer.

23. The method of claim 17, wherein the step of forming a silicon layer comprises exposing the substrate to a selected flowrate of disilane gas at a selected temperature and at a selected pressure.

24. The method of claim 17, wherein the step of forming a silicon layer comprises exposing the substrate to selected flowrates of disilane gas and a dopant gas at a selected temperature and at a selected pressure so as to form a doped silicon layer.

25. The method of claim 17, wherein said silicon layer comprises polycrystalline silicon.

26. The method of claim 17, wherein said silicon layer comprises amorphous silicon.

27. The method of claim 17, wherein the step of forming a tungsten silicide layer comprises exposing said silicon layer to a selected flowrate of tungsten hexafluoride gas at a temperature and a pressure selected to effect the displacement reaction.

28. The method of claim 17, wherein said portion of said silicon layer comprises the entire silicon layer.

29. The method of claim 17, wherein the steps of forming a silicon layer and forming a tungsten silicide layer occur in the same reactor.

30. The method of claim 17, wherein the steps of forming a silicon layer and forming a tungsten silicide layer occur in a plurality of reactors of substantially similar configuration.

31. The method of claim 30, wherein said plurality of reactors comprise a cluster tool.

32. A process of forming a gate electrode on a semiconductor substrate, comprising:

depositing a silicon layer on a substrate in a reactor chamber; and

replacing at least a portion of silicon atoms in the silicon layer with atoms to form a metallic layer comprising tungsten by direct substitution within the same reactor chamber, wherein the metallic layer comprises tungsten silicide.

33. The process of claim 32, further comprising patterning the silicon layer and metallic layer to define the gate electrode.

34. A method of forming a gate stack over a semiconductor substrate, comprising:

forming a gate dielectric layer on the semiconductor substrate;

depositing a silicon layer directly over the gate dielectric layer with the substrate positioned in a chemical vapor deposition chamber;

selectively depositing a tungsten layer on the silicon layer with the substrate positioned in a chamber of substantially the same configuration;

annealing to react the tungsten layer with underlying silicon to form a tungsten silicide layer; and

patterning the gate stack after selectively depositing.

35. The method of claim 34, wherein depositing the polysilicon layer and selectively depositing the tungsten layer are conducted in the same chamber.

36. The method of claim 34, wherein depositing the polysilicon layer and selectively depositing the tungsten layer are conducted in different chambers within a cluster tool.

37. A process of forming a gate electrode on a semiconductor substrate, comprising:

depositing a silicon layer on a substrate in a reactor chamber;

replacing at least a substantial portion of the silicon atoms in the silicon layer with tungsten atoms by direct substitution prior to patterning the gate electrode;

annealing the silicon and elemental tungsten layers to form a tungsten silicide layer.