Semiconductor display device correcting system and correcting method of semiconductor display device

• US 6,335,716 B1
• Filed: 08/31/1998
• Issued: 01/01/2002
• Est. Priority Date: 09/03/1997
• Status: Expired due to Term

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Koyama, Jun, Yamazaki, Shunpei
• Primary Examiner(s): Shalwala, Bipin
• Assistant Examiner(s): PIZIALI, JEFFREY J
• Application Number:
  US09/144,538
• Time in Patent Office: 1,219 Days
• Field of Search: 345/87, 345/89, 345/58, 345/101, 345/904, 345/92, 345/98, 348/189, 348/191, 348/254, 348/674, 257/59, 257/316
• US Class Current: 345/92
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2320/0276 for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
• CPC Class Codes: G09G 2320/0693 Calibration of display systems
• CPC Class Codes: G09G 3/001 using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background slide projectors per se G03B23/00 = 42 HP
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: G09G 3/3696 Generation of voltages supplied to electrode drivers
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78636 with supplementary region or layer for improving the flatness of the device
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate

Abstract

A semiconductor display device correcting system includes a control circuit for carrying out gamma correction of a picture signal supplied from the outside and a nonvolatile memory for storing data for gamma correction. The data for gamma correction is prepared for each semiconductor display device, so that excellent gradation display can be made.

Claims

1. A semiconductor display device correcting system comprising:

means for supplying a digital picture signal;

a semiconductor display device comprising a pixel region comprising a plurality of n channel pixel TFTs, a control circuit for carrying out gamma correction of the digital picture signal, and a nonvolatile memory for storing data used in the gamma correction;

means for converting a picture displayed on the semiconductor display device into a digital signal; and

means for comparing the digital picture signal with the converted digital signal,

wherein the control circuit is constituted by TFTs, and the control circuit and the nonvolatile memory are integrally formed over the same insulating substrate as the pixel portion,

wherein the nonvolatile memory comprises a memory element constituted by a p channel FAMOS type TFT comprising a floating gate and an n channel switching TFT,

wherein gate electrodes of the plurality of n channel pixel TFTs, the floating gate, and a gate electrode of the n channel switching TFT comprise the same material, and

wherein a source electrode and a drain electrode of the memory element comprise the same material as that of a gate electrode of the p channel FAMOS type TFT.

2. A semiconductor display device correcting system according to claim 1, further comprising a volatile memory, wherein the volatile memory is constituted by TFTs and is integrally formed on the same insulating substrate as the control circuit and the memory.

5. A semiconductor display device using a semiconductor display device correcting system according to claim 1 or claim 3.

3. A semiconductor display device correcting system comprising:

means for supplying a digital picture signal;

means for converting the digital picture signal into an analog picture signal;

a semiconductor display device comprising a pixel region comprising a plurality of n channel pixel TFTs, a control circuit for carrying out gamma correction of the analog picture signal, and a nonvolatile memory for storing data used in the gamma correction;

means for converting a picture displayed on the semiconductor display device into a digital signal; and

means for comparing the digital picture signal with the converted digital signal,

wherein the control circuit is constituted by TFTs, and the control circuit and the nonvolatile memory are integrally formed over the same insulating substrate as the pixel portion;

wherein the nonvolatile memory comprises a memory element constituted by a p channel FAMOS type TFT comprising a floating gate and an n channel switching TFT,

wherein gate electrodes of the plurality of n channel pixel TFTs, the floating gate, and a gate electrode of the n channel switching TFT comprise the same material, and

wherein a source electrode and a drain electrode of the memory element comprise the same material as that of a gate electrode of the p channel FAMOS type TFT.

4. A semiconductor display device correcting system according to claim 3, further comprising a volatile memory, wherein the volatile memory is constituted by TFTs and is integrally formed on the same insulating substrate as the control circuit and the memory.

6. A correcting method of a semiconductor display device, comprising the steps of:

carrying out gamma correction of a digital picture signal inputted to a pixel portion by a control circuit;

converting the digital picture signal subjected to gamma correction into a picture;

converting the picture into a digital signal;

obtaining gamma correction data by comparing the digital picture signal with the converted digital signal to obtain a difference therebetween and by returning the difference to the step of gamma correction; and

storing the gamma correction data in a nonvolatile memory,

wherein the control circuit is constituted by TFTs, and the control circuit and the nonvolatile memory are integrally formed over the same insulating substrate as the pixel portion,

wherein the nonvolatile memory comprises a memory element constituted by a p channel FAMOS type TFT comprising a floating gate and an n channel switching TFT,

wherein said pixel portion comprises a plurality of n channel TFTs,

wherein gate electrodes of the plurality of n channel pixel TFTs, the floating gate, and a gate electrode of the n channel switching TFT comprise the same material, and

wherein a source electrode and a drain electrode of the memory element comprise the same material as that of a gate electrode of the p channel FAMOS type TFT.

7. A correcting method of a semiconductor display device, comprising the steps of:

converting a digital picture signal into an analog picture signal;

carrying out gamma correction of the analog picture signal inputted to a pixel portion by a control circuit;

converting the analog picture signal subjected to the gamma correction into a picture;

converting the picture into a digital signal;

obtaining gamma correction data by comparing the digital picture signal with the converted digital signal to obtain a difference therebetween and by returning the difference to the step of gamma correction; and

storing the gamma correction data in a nonvolatile memory,

wherein said control circuit is constituted by TFTs, and the control circuit and the nonvolatile memory are integrally formed over the same insulating substrate the pixel portion,

wherein the nonvolatile memory comprises a memory element constituted by a p channel FAMOS type TFT comprising a floating gate and an n channel switching TFT,

wherein the pixel portion comprises a plurality of n channel TFTs,

wherein gate electrodes of the plurality of n channel pixel TFTs, the floating gate, and a gate electrode of the n channel switching TFT comprise the same material, and

wherein a source electrode and a drain electrode of the memory element comprise the same material as that of a gate electrode of the p channel FAMOS type TFT.

8. An electronic device having an active matrix panel, said panel comprising:

a substrate having an insulating surface;

an active matrix circuit formed on said insulating surface;

a driver circuit for driving said active matrix circuit formed on said insulating surface;

a correction circuit operationally connected to said driver circuit;

a nonvolatile memory circuit operationally connected to said correction circuit,

wherein each of said active matrix circuit, said driver circuit, said correction circuit and said nonvolatile memory circuit are formed on said insulating surface,

wherein each of said active matrix circuit, said driver circuit, said correction circuit comprises thin film transistors,

wherein said nonvolatile memory comprises a memory element constituted by a FAMOS type thin film transistor comprising a floating gate a switching thin film transistor.

9. An electronic device according to claim 8 wherein said electronic device is a projection display system.

10. An electronic device according to claim 8 wherein said electronic device is a video camera.

11. An electronic device according to claim 8 wherein said electronic device is a still camera.

12. An electronic device according to claim 8 wherein said electronic device is a head mount display.

13. An electronic device according to claim 8 wherein said electronic device is a car navigation system.

14. An electronic device according to claim 8 wherein said electronic device is a personal computer.

15. An electronic device according to claim 8 wherein said electronic device is a portable information terninal.

16. An electronic device according to claim 8 wherein said FAMOS type thin film transistor is a p-channel FAMOS type thin film transistor and said switching thin film transistor is an n-channel switching thin film transistor.

17. An electronic device according to claim 8 wherein gate electrodes of said thin film transistors, said floating gate, and a gate electrode of said switching thin film transistor comprise the same material.

18. An electronic device according to claim 8 wherein a source electrode and a drain electrode of said memory element comprise the same material as that of a gate electrode of said FAMOS type thin film transistor.

19. An electronic device according to claim 8 wherein each of said thin film transistors, said FAMOS type thin film transistor, and said switching thin film transistor comprises a semiconductor layer comprising a source region, a drain region, a low concentration impurity region, and a channel region.