Video output apparatus

• US 6,335,764 B1
• Filed: 02/25/1999
• Issued: 01/01/2002
• Est. Priority Date: 04/09/1998
• Status: Expired due to Term

• Current Assignee: Socionext Inc.
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Iwasa, Masaru, Fujii, Eiko, Hashimoto, Tsutomu
• Primary Examiner(s): Lee, Michael
• Application Number:
  US09/257,044
• Time in Patent Office: 1,041 Days
• Field of Search: H04/N.545, 348/563, 348/564, 348/565, 348/566, 348/567, 348/569, 348/584, 348/585, 348/588, 348/586, 348/589, 348/518, 348/501, 348/554, 348/555, 348/558
• US Class Current: 348/565
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 5/14 Display of multiple viewports
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence
• CPC Class Codes: H04N 21/4316 for displaying supplemental content in a region of the screen, e.g. an advertisement in a separate window
• CPC Class Codes: H04N 21/44004 involving video buffer management, e.g. video decoder buffer or video display buffer
• CPC Class Codes: H04N 21/4435 Memory management allocation of memory to service a request G06F9/5016; addressing or allocating within memory systems or architectures G06F12/02
• CPC Class Codes: H04N 21/485 End-user interface for client configuration
• CPC Class Codes: H04N 5/445 for displaying additional information H04N5/50 takes precedence
• CPC Class Codes: H04N 5/44504 Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits
• CPC Class Codes: H04N 5/45 Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen

Abstract

A video output apparatus comprises: video data processor for processing plural pieces of video data of different types and outputting the resulting video data to a monitor; video processing delay detector for detecting whether processing for the plural pieces of video data performed by the video data processor is completed in real time when it is output to the monitor; and video data processing controller for controlling the video data processor so that the processing performed by the video data processor which is allocated for on line period is reduced when the video processing delay detector detects delay in processing.

Claims

1. A video output apparatus comprising:

video data processing means for processing plural pieces of video data of different types and outputting the resulting video data to a monitor;

video processing delay detecting means for detecting delay by deciding whether or not processing for the plural pieces of video data performed by the video data processing means is completed in real time when it is output to the monitor; and

video data processing control means for controlling the video data processing means so that the processing performed by the video data processing means which is to be allocated for one line period is reduced when the video processing delay detecting means detects delay.

2. The video output apparatus of claim 1 wherein

the video data processing control means controls the video data processing means by setting a priority of the video data processing when the processing is reduced.

3. The video output apparatus of claim 2 wherein

the priority is determined according to distance from a user'"'"'s view point to a display image on the monitor.

4. The video output apparatus of claim 2 wherein

the priority is determined according to display information set in the video data.

5. The video output apparatus of claim 1 wherein at least one of the processing for the plural pieces of video data to be performed during one line period is divided into plural processes.

6. The video output apparatus of claim 1 wherein

the video processing delay detecting means detects delay in units, each unit comprising either a predetermined number of fields or a predetermined number of frames.

7. The video output apparatus of claim 1 wherein

the video processing delay detecting means detects delay in units, each unit comprising a predetermined number of lines.

8. The video output apparatus of claim 1 wherein

the video data processing control means skips at least one part of video data processing among the processing for the plural pieces of video data, to reduce the processing.

9. The video output apparatus of claim 5 wherein

the video data processing control means skips at least one part of video data processing among the processing for the plural pieces of video data, to reduce the processing.