Single chip CMOS transmitter/receiver

• US 6,335,952 B1
• Filed: 07/24/1998
• Issued: 01/01/2002
• Est. Priority Date: 07/24/1998
• Status: Expired due to Term

• Current Assignee: GCT Semiconductor Incorporated
• Original Assignee: GCT Semiconductor Incorporated
• Inventors: Jeong, Deog-Kyoon, Lee, Kyeongho
• Primary Examiner(s): Pham, Chi
• Assistant Examiner(s): Bayard, Emmanuel
• Application Number:
  US09/121,601
• Time in Patent Office: 1,257 Days
• Field of Search: 375/215, 375/280, 375/294, 375/331, 375/332, 375/327, 375/376, 375/373, 329/307, 329/325, 329/360, 327/156, 327/147, 455/260, 455/180.3, 331/1
• US Class Current: 375/327
• CPC Class Codes: H03D 7/1441 using field-effect transistors H03D7/145 takes precedence
• CPC Class Codes: H03H 11/22 providing two or more phase shifted output signals, e.g. n-phase output
• CPC Class Codes: H03H 2011/0494 Complex filters
• CPC Class Codes: H03K 9/00 Demodulating pulses which have been modulated with a continuously-variable signal
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/1974 for fractional frequency division
• CPC Class Codes: H04B 1/403 using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency

Abstract

A single chip RF communication system and method is provided including a transmitter and a receiver. The RF communication system in accordance with the present invention includes an antenna for receiving transmitting RF signals, a PLL for generating multi-phase clock signals having a frequency different from a carrier frequency in response to the multi-phase clock signals and a reference signal having the carrier frequency, a demodulation-mixing unit for mixing the received RF signals with the multi-phase clock signals having the frequency different from the carrier frequency to output the RF signals having a frequency reduced by the carrier frequency and an A/D converting unit for converting the RF signals from the mixing unit into digital signals.

Claims

1. A communication system, comprising:

a receiver unit that receives signals including selected signals having a carrier frequency;

a single PLL that generates more than two multi-phase clock signals having a frequency different from the carrier frequency, wherein the multi-phase clock signals are combined to generate a plurality of local oscillator signals having a second frequency higher than the frequency; and

a demodulation-mixer that mixes the received selected signals with the more than two multi-phase clock signals to output the selected signals having a frequency reduced by the carrier frequency, wherein each of the local oscillator signals demodulate one of an I carrier frequency signal and a Q carrier frequency signal.

2. The communication system of claim 1, wherein the frequency is smaller than the carrier frequency, and wherein the RF communication system is formed on a single CMOS chip.

3. The communication system of claim 1, wherein the PLL includes a clock generator.

4. The communication system of claim 3, wherein the clock generator is a voltage controlled oscillator.

5. The communication system of claim 1, wherein the receiver unit is a transceiver, further comprising:

a modulation mixer that mixes the multi-phase clock signals, which operate as the local oscillator signals, with transmission data to modulate the transmission data; and

a power amplifier that amplifies the modulated transmission data and transmits the data to the transceiver for transmission.

6. The communication system of claim 1, further comprising:

a RF filter coupled to the receiver unit that filters the received selected signals;

a low noise amplifier coupled to the RF filter that amplifies the filtered selected signals with a gain; and

a low pass filter coupled to the demodulation mixer that filters the selected signals having the frequency reduced by the carrier frequency.

7. The communication system as claimed in claim 1, further comprising:

an A/D converting unit that converts the selected signals from the demodulation-mixer into digital signals; and

a discrete-time signal processing unit that receives the digital signals.

8. The communication system of claim 1, wherein the communication system is a RF receiver portion, wherein the selected signals are RF signals, wherein the multi-phase clock signals have a frequency of (2*carrier frequency/N) where N is a positive integer greater than two, and wherein the RF communication system is formed on a single CMOS chip.

9. The communication system of claim 1, wherein the RF communication system is operated with the carrier frequency greater than 1 GHz.

18. The communication system of claim 1, wherein the demodulation mixer comprises a first mixer array and a second mixer array, each of the first and second mixer arrays including a plurality of multiple input mixers.

19. The communication system of claim 1, wherein the demodulation mixer comprises a first mixer array and a second mixer array, each of the first and second mixer arrays having a plurality of mixer stages, each of the mixer stages having at least one multiple input mixer.

20. The communication system of claim 19, wherein output signals from the at least one multiple input mixer of a first of the plurality of stages are input into at least one multiple input mixer of a second of the plurality of stages.

21. The communication system of claim 1, wherein the more than two multi-phase clock signals comprise a plurality of pairs of multi-phase clock signals, each of the plurality of pairs including an I carrier frequency signal and a Q carrier frequency signal.

22. The communication system of claim 1, wherein a reference signal is formed by combining the more than two multi-phase clock signals.

10. A single chip RF communication system, comprising:

a transceiver for receiving and transmitting RF signals;

a single PLL for generating a plurality of 2N-phase clock signals having a substantially identical frequency 2*f₀/N smaller than a carrier frequency f_o, wherein N is a positive integer as a phase number;

a demodulation mixing unit for mixing the RF signals from the transceiver with the plurality of 2N-phase clock signals from the PLL to output the RU signals having a frequency reduced by the carrier frequency, wherein the demodulation mixer comprises a plurality of two input mixers, wherein the plurality of 2N-phase clock signals are combined to demodulate at least one of an I carrier frequency signal and a Q carrier frequency signal; and

an A/D converting unit for converting the RF signals from the demodulation mixing unit into digital signals.

11. The single chip RF communication system of claim 10, wherein the demodulation mixing unit includes a first mixer array comprising one half of the two input mixers and a second mixer array comprising the other half of the two input mixers, and each mixer array inputs each corresponding N-phase clock signals of the 2N-phase clock signals together with the RF signals.

12. The single chip RF communication system of claim 10, wherein each mixer array comprises multi-stages of mixers, each stage includes at least one two-input mixer, and a first stage of the multi-stages inputs the RF signals and N-phase clock signals.

13. The single chip RF communication system of claim 12, wherein the multi-stages have a corresponding reducing number of mixers K1>

K2>

K3>

. . . >

Ki, where K1 is the first stage, K2 is a second stage, K3 is a third stage, and Ki is a with stage.

23. The single chip RF communication system of claim 10, wherein the demodulation mixing unit comprises a first mixer array and a second mixer array, each of the first and second mixer arrays including a plurality of multiple input mixers.

24. The single chip RF communication system of claim 10, wherein the demodulation mixing unit comprises a first mixer array and a second mixer array, each of the first and second mixer arrays having a plurality of mixer stages, each of the mixer stages having at least one multiple input mixer.

25. The single chip RF communication system of claim 24, wherein output signals from the at least one multiple input mixer of a first of the plurality of stages are input into at least one multiple input mixer of a second of the plurality of stages.

26. The single chip RF communication system of claim 10, wherein local oscillator signals are formed by combining the plurality of 2N-phase clock signals.

27. The single chip RF communication system of claim 10, wherein the plurality of 2N-phase clock signals are divided into a first plurality of clock signals combined to form an I carrier frequency, and a second plurality of clock signals combined to form a Q carrier frequency.

30. The single chip RF communication system of claim 10, wherein the RF communication system is formed using CMOS technology and operates with the carrier frequency greater than 1 GHz.

14. A method of operating a RF communication system, comprising:

receiving signals including selected signals having a carrier frequency;

generating more than two multi-phase clock signals each having a substantially identical frequency different from the carrier frequency, wherein the multi-phase clock signals are combined to generate a plurality of local oscillator signals having a second frequency higher than the frequency; and

mixing the received carrier frequency selected signals with the more than two multi-phase clock signals to output demodulated selected signals having a frequency reduced from the carrier frequency so that corresponding ones of the local oscillator signals combined from the more than two multi-phase clock signals demodulate one of a first carrier frequency signal and a second carrier frequency signal.

15. The method of claim 14, wherein the frequency is smaller than the carrier frequency, wherein the generating step uses a PLL that includes a voltage controlled oscillator, and wherein the first carrier frequency signal is an I carrier frequency signal and the second carrier frequency signal is a Q carrier frequency signal.

16. The method of claim 14, further comprising:

RF filtering the received selected signals;

amplifying the filtered selected signals with a gain; and

low pass filtering the demodulated selected signals having the frequency reduced to baseband;

A/D converting the low pass filtered frequency reduced selected signals into digital signals; and

discrete-time signal processing the digital signals.

17. The method of claim 14, further comprising:

modulation mixing the multi-phase clock signals combined as the local oscillator signals with transmission data to modulate the transmission data; and

power amplifying the modulated transmission data and transmitting the data to the transceiver for transmission.

28. The method of claim 14, further comprising combining the more than two multi-phase clock signals to form a reference signal.

29. The method of claim 14, wherein the RF communication system is formed using CMOS technology and operates with the carrier frequency greater than 1 GHz.

31. A communication system, comprising:

receiving means for receiving signals including selected signals having a carrier frequency;

single PLL means for generating more than two multi-phase clock signals having a first frequency smaller than the carrier frequency; and

demodulation-mixer means for combining the multi-phase clock signals to form a plurality of local oscillator signals that each have a second frequency higher than the first frequency and for mixing with the received selected signals to output the selected signals having a frequency reduced from the carrier frequency, wherein the local oscillator signals demodulate corresponding ones of an I carrier frequency signal and a Q carrier frequency signal.

32. A single chip RF communication system, comprising:

transceiver means for receiving and transmitting RF signals;

single PLL means for generating a plurality of 2N-phase clock signals having a substantially identical frequency 2*f₀/N smaller than a carrier frequency f_o, wherein N is a positive integer as a phase number; and

demodulation mixing means for mixing the RF signals from the transceiver means with the plurality of 2N-phase clock signals from the PLL means to output the RF signals having a frequency reduced by the carrier frequency, wherein the demodulation mixer means comprises a first plurality of two input mixer means and a second plurality of two input mixer means, wherein the plurality of 2N-phase clock signals are combined to demodulate at least one of an I carrier frequency signal and a Q carrier frequency signal.