Method and apparatus for gate-level simulation of synthesized register transfer level design with source-level debugging

• US 6,336,087 B2
• Filed: 07/24/1998
• Issued: 01/01/2002
• Est. Priority Date: 07/24/1998
• Status: Expired due to Term

• Current Assignee: Mentor Graphics Corporation (Siemens AG), Mentor Graphics Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Burgun, Luc M., Raynaud, Alain
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): THOMSON, WILLIAM D
• Application Number:
  US09/122,493
• Publication Number:
  US 20010011212A1
• Time in Patent Office: 1,257 Days
• Field of Search: 703/14, 703/15, 703/16, 703/17, 703/20, 703/27, 703/28, 716/4, 716/16, 716/2, 716/3
• US Class Current: 703/15
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation

Abstract

Register transfer level (RTL) source code is synthesized to generate a gate-level representation and to generate instrumentation logic corresponding to one or more statements in the RTL source code. The instrumentation logic comprises logic circuitry in addition to that of the gate-level representation. The instrumentation logic indicates an execution status for the corresponding RTL statement(s) during gate-level simulation.

Claims

1. A method comprising:

receiving an original synthesizable register transfer level (RTL) source code; and

synthesizing the original RTL source code to generate a gate-level representation of the original RTL source code and also to generate instrumentation logic corresponding to at least one synthesizable statement in the original RTL source code, the instrumentation logic comprising logic circuitry in addition to logic circuitry of the gate-level representation of the original RTL source code, and the instrumentation logic to indicate an execution status of the at least one synthesizable statement of the original RTL source code during a gate-level simulation of the gate-level representation and the instrumentation logic.

2. The method of claim 1 further comprising:

synthesizing the original RTL source code to generate instrumentation information, wherein the instrumentation information comprises cross-reference instrumentation data.

3. The method of claim 1 wherein the gate-level representation of the original RTL source code and the instrumentation logic comprise a single gate-level design representation.

4. The method of claim 1 wherein synthesizing the original RTL source code to generate the gate-level representation and the instrumentation logic comprises modifying the RTL source code prior to synthesis.

5. The method of claim 1 wherein synthesizing the original RTL source code to generate the instrumentation logic comprises modifying a post parsed data structure.

6. The method of claim 1 wherein the original synthesizable RTL source code includes edge-sensitive statements.

7. The method of claim 1 wherein the original synthesizable RTL source code includes level sensitive statements.

8. The method of claim 1 further comprising:

synthesizing the original RTL source code to generate instrumentation information, wherein the instrumentation information is generated for each of a list of synthesizable statements in the original RTL source code.

9. The method of claim 2 further comprising incrementing an execution count of the at least one synthesizable statement when cross reference instrumentation data of the corresponding instrumentation information indicates the at least one synthesizable statement is active.

10. The method of claim 1 further comprising displaying the at least one synthesizable statement as a highlighted statement during simulation in accordance with an execution status of the synthesizable statement as indicated by the instrumentation logic.

11. The method of claim 2 wherein the instrumentation information further utilizes selected logic of the gate-level representation of the RTL source.

12. A machine readable medium having stored therein machine executable instructions, wherein when executed the instructions enable the machine to:

receive an original synthesizable register transfer level (RTL) source code; and

synthesize the original RTL source code to generate a gate-level representation of the original RTL source code and also to generate instrumentation logic corresponding to at least one synthesizable statement in the original RTL source code, the instrumentation logic comprising logic circuitry in addition to logic circuitry of the gate-level representation of the original RTL source code, and the instrumentation logic to indicate an execution status of the at least one synthesizable statement of the original RTL source code during a gate-level simulation of the gate-level representation and the instrumentation logic.

13. The machine readable medium of claim 12 wherein the instructions further enable the machine to:

synthesize the original RTL source code to generate instrumentation information, wherein the instrumentation information comprises cross-reference instrumentation data.

14. The machine readable medium of claim 12 wherein synthesizing the original RTL source code to generate the gate-level representation and the instrumentation logic comprises modifying the RTL source code prior to synthesis.

15. The machine readable medium of claim 12 wherein synthesizing the original RTL source code to generate the instrumentation logic comprises modifying a post parsed data structure.

16. The machine readable medium of claim 12 wherein the instructions further enable the machine to:

synthesize the original RTL source code to generate instrumentation information, wherein the instrumentation information is generated for each of a list of synthesizable statements in the original RTL source code.

17. The machine readable medium of claim 13 further comprising incrementing an execution count of the at least one synthesizable statement when cross reference instrumentation data of the corresponding instrumentation information indicates the at least one synthesizable statement is active.

18. The machine readable medium of claim 12 further comprising displaying the at least one synthesizable statement as a highlighted statement during simulation in accordance with an execution status of the synthesizable statement as indicated by the instrumentation logic.