Apparatus and method for enhancing data transfer rates using transfer control blocks

• US 6,336,150 B1
• Filed: 12/31/1998
• Issued: 01/01/2002
• Est. Priority Date: 10/30/1998
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Springberg, David M., Weston-Lewis, Graeme M., Ellis, Jackson L.
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Perveen, Rehana
• Application Number:
  US09/223,871
• Time in Patent Office: 1,097 Days
• Field of Search: 710/4, 710/18, 710/5, 710/33
• US Class Current: 710/5
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

The present invention includes a Command Queuing Engine (CQE) that is a firmware-assist block which processes some of the firmware tasks related to command and context management preferably for SCSI. When enabled, CQE will decode SCSI commands as they arrive, and determine if DMA contexts can be automatically configured and started to transfer the data for those commands. CQE can also program DMA contexts to automatically return status information either after the disk has completed a transfer (as in non-cached writes) or after the DMA transfer is completed (as in reads or cached writes). CQE also utilizes a buffer-based linked-list to queue the SCSI commands as they arrive for future DMA context configuration. The present invention provides automated recognition and linking of commands belonging to a common thread, i.e., are sequential. The present invention also provides extensive thread boundary information and flexible firmware control for reordering commands. Automatic TE entry generation and storage to buffer memory, and automatic TE retrieval from the buffer memory and execution of entire command threads are further features provided by the present invention. As a result, bus command response latency is decreased by reducing the delay for the command to be started and at the end of the data transfer for status to be send. Disk efficiency is increased by reducing the latency to back-fill or empty a buffer memory segment of data that will be transferred. Furthermore, the present invention is a low-cost trade-off between hardware and firmware functionality.

Claims

1. A method of enhancing data rates comprising the steps of:

(A) generating a transfer control block list in response to a first command of a thread of sequential commands, said transfer control block list comprising (i) a first pointer to a first transfer extend entry of said thread and (ii) a second pointer to a last transfer extend entry of said thread; and

(B) updating said last transfer extend entry in response to a second command sequential to said first command.

2. The method of claim 1 wherein the transfer control block list is derived from a first command of a thread.

3. The method of claim 2 wherein the transfer control block list includes initiator ID, read/write, QTag, LBA, length.

4. The method of claim 1 wherein the transfer control block list includes first and final logical addresses of a thread.

5. A method of automating the transfer of commands comprising the steps of:

generating a corresponding transfer control block for a command;

determining whether another command is sequential to a previous command;

generating another corresponding transfer control block if the other command is not sequential; and

updating said corresponding transfer control block if the other command is sequential.

6. The method of claim 5 further comprising the step of determining whether any command is a read or a write command.

7. The method of claim 5 wherein the step of determining whether the other command is sequential includes comparing the other command with the final logical addresses of other transfer control blocks.

8. The method of claim 5 wherein corresponding transfer control blocks are generated for read and write commands.

9. The method of claim 5 wherein the step of determining whether the other command is sequential includes comparing the other command with an immediately preceding command.

10. A method of transferring data comprising the steps of:

generating a transfer control block for a first thread associated with at least a one command; and

generating a transfer control block for a second thread associated with at least another command; and

determining if an additional command is sequential to one of the first or second threads.

11. The method of claim 10 further including the step of modifying the transfer control block for one of the first and second threads if the additional command is within an address range.

12. The method of claim 10 further including the step of modifying the transfer control block for one of the first and second threads if the additional command is immediately sequential.

13. A data transfer apparatus comprising:

a data controller;

a microprocessor coupled to the data controller; and

local storage coupled to the microprocessor, wherein the local storage includes at least one transfer control block that controls the transfer of data within the data controller, said transfer control block comprising (i) a first pointer to a first transfer extend entry of a thread of sequential commands and (ii) a second pointer to a last transfer extend entry of said thread.

14. The apparatus of claim 13 wherein the transfer control block includes first and final logical addresses of a thread.

15. The apparatus of claim 13 wherein the transfer control block is modified responsive to a sequential command.

16. The apparatus of claim 13 wherein another transfer control block is generated responsive to a non-sequential command.