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Deterministic error notification and event reordering mechanism provide a host processor to access complete state information of an interface controller for efficient error recovery

  • US 6,336,157 B1
  • Filed: 10/30/1998
  • Issued: 01/01/2002
  • Est. Priority Date: 10/30/1998
  • Status: Expired due to Fees
First Claim
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1. A method for halting operation of an interface controller within a network communications port in response to a signal from a host processor, a host processor together with the network communications port composing a network communications node in which the host processor communicates with the interface controller via shared data structures and control registers, the method comprising:

  • receiving the signal by the host processor;

    suspending processing of data being transferred to the interface controller from the communications network;

    suspending processing of data being transferred from the host processor to the communications network;

    flushing cached information from the shared data structures from the interface controller back to the shared data structures;

    processing outgoing data transfer operations pipelined within the interface controller; and

    sending an indication to the host processor that the operation of the interface controller has halted, that the shared data structures contain the complete state information of the interface controller and information about current data transfer operations, and that the host processor will now have access to the shared data structures without additional interrupts or messages from the interface controller.

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