Memory based I/O decode arrangement, and system and method using the same
First Claim
1. An input/output (I/O) decode arrangement comprising:
- an I/O decode map in a form of a memory block and containing, before start of any bus I/O transactions, I/O address decode information for positive claiming of bus transaction ownership, for at least a portion of possible I/O addresses in a system, with said I/O decode map sub-divided in its entirety into a plurality of sub-byte portions, and with each sub-byte portion of said I/O decode map containing positive claiming information for a different one of said at least a portion of said possible I/O addresses in the system.
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Abstract
An input/output (I/O) decode arrangement including an I/O decode map in a form of a memory block and containing, before start of any bus I/O transactions, I/O address decode information useable for I/O address decoding for bus transaction ownership, for at least a portion of, and preferably all, possible I/O addresses in a system. Further included are: an I/O decode map pointer adapted to point to a memory address where said I/O decode map is located; an I/O decode cache adapted to cache said decode information with respect to ones of I/O addresses of which accessing has been previously performed with respect to said I/O decode map; and an I/O snooper/storer adapted to snoop said I/O decode map with any I/O address to retrieve said decode information corresponding to said I/O address, and further adapted to store retrieved said decode information into said I/O decode cache. The I/O decode map can be located within at least one of system management memory (SMM) or basic input/output system (BIOS) memory space. Implementation can further be made in a computing system and method.
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Citations
23 Claims
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1. An input/output (I/O) decode arrangement comprising:
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an I/O decode map in a form of a memory block and containing, before start of any bus I/O transactions, I/O address decode information for positive claiming of bus transaction ownership, for at least a portion of possible I/O addresses in a system, with said I/O decode map sub-divided in its entirety into a plurality of sub-byte portions, and with each sub-byte portion of said I/O decode map containing positive claiming information for a different one of said at least a portion of said possible I/O addresses in the system. - View Dependent Claims (2, 3, 4, 5, 6, 7)
an I/O decode map pointer adapted to point to a memory address where said I/O decode map is located;
an I/O decode cache adapted to cache said decode information with respect to ones of I/O addresses of which accessing has been previously performed with respect to said I/O decode map; and
an I/O snooper/storer adapted to snoop said I/O decode map with any I/O address to retrieve said decode information corresponding to said I/O address, and further adapted to store retrieved said decode information into said I/O decode cache.
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8. An input/output (I/O) decode arrangement comprising:
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an I/O decode map means in a form of a memory means for storing, before start of any bus I/O transactions, I/O address decode information for positive claiming of bus transaction ownership, for at least a portion of possible I/O addresses in a system, with said I/O decode map means sub-divided in its entirety into a plurality of sub-byte portions, and with each sub-byte portion of said I/O decode map means containing positive claiming information for a different one of said at least a portion of said possible I/O addresses in the system. - View Dependent Claims (9, 10, 11, 12, 13, 14)
an I/O decode map pointer means for pointing to a memory address where said I/O decode map means is located;
an I/O decode cache means for caching said decode information with respect to ones of I/O addresses of which accessing has been previously performed with respect to said I/O decode map means; and
an I/O snooper/storer means for snooping said I/O decode map means with any I/O address to retrieve said decode information corresponding to said I/O address, and for storing retrieved said decode information into said I/O decode cache means.
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15. A computing system comprising:
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a microprocessor;
a memory;
at least one bus;
a plurality of agents connected to said at least one bus, with each agent having at least one I/O address assigned thereto; and
an input/output (I/O) decode arrangement comprising;
an I/O decode map in a form of a memory block and containing, before start of any bus I/O transactions, I/O address decode information for effecting positive claiming of bus transaction ownership, for at least a portion of possible I/O addresses in the computing system, with said I/O decode map sub-divided in its entirety into a plurality of sub-byte portions, and with each sub-byte portion of said I/O decode map containing positive claiming information for a different one of said at least a portion of said possible I/O addresses in the system. - View Dependent Claims (16, 17, 18, 19, 20, 21)
an I/O decode map pointer adapted to point to a memory address where said I/O decode map is located;
an I/O decode cache adapted to cache said decode information with respect to ones of I/O addresses of which accessing has been previously performed with respect to said I/O decode map; and
an I/O snooper/storer adapted to snoop said I/O decode map with any I/O address to retrieve said decode information corresponding to said I/O address, and further adapted to store retrieved said decode information into said I/O decode cache.
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22. An input/output (I/O) decode method comprising the steps of:
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providing an I/O decode map in a form of a memory block and which contains, before start of any bus I/O transactions, I/O address decode information for positive claiming of bus transaction ownership, for at least a portion of possible I/O addresses in a system, with said I/O decode map sub-divided in its entirety into a plurality of sub-byte portions, and with each sub-byte portion of said I/O decode map containing positive claiming information for a different one of said at least a portion of said possible I/O addresses in the system; and
using said I/O address decode information for performing address decoding for bus transaction ownership. - View Dependent Claims (23)
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Specification