Memory based I/O decode arrangement, and system and method using the same

• US 6,336,158 B1
• Filed: 10/30/1998
• Issued: 01/01/2002
• Est. Priority Date: 10/30/1998
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Martwick, Andrew W.
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): SCHUSTER, KATHARINA W
• Application Number:
  US09/182,443
• Time in Patent Office: 1,159 Days
• Field of Search: 710/129, 710/128, 710/3, 710/109, 710/101, 710/103, 710/1, 710/9, 710/10, 710/36, 710/104, 710/107, 710/113, 710/126, 711/100, 709/250, 709/201, 717/11, 370/428, 345/515
• US Class Current: 710/104
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

An input/output (I/O) decode arrangement including an I/O decode map in a form of a memory block and containing, before start of any bus I/O transactions, I/O address decode information useable for I/O address decoding for bus transaction ownership, for at least a portion of, and preferably all, possible I/O addresses in a system. Further included are: an I/O decode map pointer adapted to point to a memory address where said I/O decode map is located; an I/O decode cache adapted to cache said decode information with respect to ones of I/O addresses of which accessing has been previously performed with respect to said I/O decode map; and an I/O snooper/storer adapted to snoop said I/O decode map with any I/O address to retrieve said decode information corresponding to said I/O address, and further adapted to store retrieved said decode information into said I/O decode cache. The I/O decode map can be located within at least one of system management memory (SMM) or basic input/output system (BIOS) memory space. Implementation can further be made in a computing system and method.

Claims

1. An input/output (I/O) decode arrangement comprising:

an I/O decode map in a form of a memory block and containing, before start of any bus I/O transactions, I/O address decode information for positive claiming of bus transaction ownership, for at least a portion of possible I/O addresses in a system, with said I/O decode map sub-divided in its entirety into a plurality of sub-byte portions, and with each sub-byte portion of said I/O decode map containing positive claiming information for a different one of said at least a portion of said possible I/O addresses in the system.

2. An arrangement as claimed in claim 1, wherein said I/O decode map more specifically contains decode information for all possible I/O addresses in the system.

3. An arrangement as claimed in claim 2, wherein if there are 2^M (where M is an integer) possible I/O addresses in the system, said I/O decode map more specifically has 2^M−

N addressable memory locations (where N is an integer), and 2^N bits per memory location, with each I/O decode map bit containing said I/O address decode information for a different one of said possible I/O addresses in the system.

4. An arrangement as claimed in claim 3, wherein if a bus transaction address has M bits, said I/O decode map is adapted such that a first M−

N subset of said M bits determines an I/O decode map address for accessing said 2^N bits within said I/O decode map which corresponds to said bus transaction address, and an unused N subset of said M bits determines a said I/O decode map bit within an accessed said 2^N bits which corresponds to said bus transaction address.

5. An arrangement as claimed in claim 3, wherein if there are 2^M (where M is 16) possible I/O addresses in the system, said I/O decode map more specifically has 2^M−

N addressable memory locations (where N is

     3), and 2^N bits per memory location, with each I/O decode map bit containing said I/O address decode information for a different one of said possible I/O addresses in the system.

6. An arrangement as claimed in claim 1, wherein said I/O decode map more specifically is located within at least one of system management memory (SMM) or basic input/output system (BIOS) memory space.

7. An arrangement as claimed in claim 1, further comprising:

an I/O decode map pointer adapted to point to a memory address where said I/O decode map is located;

an I/O decode cache adapted to cache said decode information with respect to ones of I/O addresses of which accessing has been previously performed with respect to said I/O decode map; and

an I/O snooper/storer adapted to snoop said I/O decode map with any I/O address to retrieve said decode information corresponding to said I/O address, and further adapted to store retrieved said decode information into said I/O decode cache.

8. An input/output (I/O) decode arrangement comprising:

an I/O decode map means in a form of a memory means for storing, before start of any bus I/O transactions, I/O address decode information for positive claiming of bus transaction ownership, for at least a portion of possible I/O addresses in a system, with said I/O decode map means sub-divided in its entirety into a plurality of sub-byte portions, and with each sub-byte portion of said I/O decode map means containing positive claiming information for a different one of said at least a portion of said possible I/O addresses in the system.

9. An arrangement as claimed in claim 8, wherein said I/O decode map means more specifically is for storing decode information for all possible I/O addresses in the system.

10. An arrangement as claimed in claim 9, wherein if there are 2^M (where M is an integer) possible I/O addresses in the system, said I/O decode map means more specifically has 2^M−

N addressable memory locations (where N is an integer), and 2^N bits per memory location, with each I/O decode map bit containing said I/O address decode information for a different one of said possible I/O addresses in the system.

11. An arrangement as claimed in claim 10, wherein if a bus transaction address has M bits, said I/O decode map is adapted such that a first M−

N subset of said M bits determines an I/O decode map address for accessing a said 2^N bits within said I/O decode map means which corresponds to said bus transaction address, and an unused N subset of said M bits determines a said I/O decode map bit within an accessed said 2^N bits which corresponds to said bus transaction address.

12. An arrangement as claimed in claim 10, wherein if there are 2^M (where M is 16) possible I/O addresses in the system, said I/O decode map means more specifically has 2^M−

N addressable memory locations (where N is

     3), and 2^N bits per memory location, with each I/O decode map bit containing said I/O address decode information for a different one of said possible I/O addresses in the system.

13. An arrangement as claimed in claim 8, wherein said I/O decode map means more specifically is located within at least one of system management memory (SMM) or basic input/output system (BIOS) memory space.

14. An arrangement as claimed in claim 8, further comprising:

an I/O decode map pointer means for pointing to a memory address where said I/O decode map means is located;

an I/O decode cache means for caching said decode information with respect to ones of I/O addresses of which accessing has been previously performed with respect to said I/O decode map means; and

an I/O snooper/storer means for snooping said I/O decode map means with any I/O address to retrieve said decode information corresponding to said I/O address, and for storing retrieved said decode information into said I/O decode cache means.

15. A computing system comprising:

a microprocessor;

a memory;

at least one bus;

a plurality of agents connected to said at least one bus, with each agent having at least one I/O address assigned thereto; and

an input/output (I/O) decode arrangement comprising;

an I/O decode map in a form of a memory block and containing, before start of any bus I/O transactions, I/O address decode information for effecting positive claiming of bus transaction ownership, for at least a portion of possible I/O addresses in the computing system, with said I/O decode map sub-divided in its entirety into a plurality of sub-byte portions, and with each sub-byte portion of said I/O decode map containing positive claiming information for a different one of said at least a portion of said possible I/O addresses in the system.

16. A computing system as claimed in claim 15, wherein said I/O decode map more specifically contains decode information for all possible I/O addresses in the computing system.

17. A computing system as claimed in claim 16, wherein if there are 2^M (where M is an integer) possible I/O addresses in the computing system, said I/O decode map more specifically has 2^M−

N addressable memory locations (where N is an integer), and 2^N bits per memory location, with each I/O decode map bit containing said I/O address decode information for a different one of said possible I/O addresses in the computing system.

18. A computing system as claimed in claim 17, wherein if a bus transaction address has M bits, said I/O decode map is adapted such that a first M−

N subset of said M bits determines an I/O decode map address for accessing a said 2^N bits within said I/O decode map which corresponds to said bus transaction address, and an unused N subset of said M bits determines a said I/O decode map bit within an accessed said 2^N bits which corresponds to said bus transaction address.

19. A computing system as claimed in claim 17, wherein if there are 2^M (where M is 16) possible I/O addresses in the computing system, said I/O decode map more specifically has 2^M−

N addressable memory locations (where N is

     3), and 2^N bits per memory location, with each I/O decode map bit containing said I/O address decode information for a different one of said possible I/O addresses in the computing system.

20. A computing system as claimed in claim 15, wherein said I/O decode map more specifically is located within at least one of system management memory (SMM) or basic input/output system (BIOS) memory space of the computing system.

21. A computing system as claimed in claim 15, wherein said input/output (I/O) decode arrangement further comprises:

an I/O decode map pointer adapted to point to a memory address where said I/O decode map is located;

an I/O decode cache adapted to cache said decode information with respect to ones of I/O addresses of which accessing has been previously performed with respect to said I/O decode map; and

an I/O snooper/storer adapted to snoop said I/O decode map with any I/O address to retrieve said decode information corresponding to said I/O address, and further adapted to store retrieved said decode information into said I/O decode cache.

22. An input/output (I/O) decode method comprising the steps of:

providing an I/O decode map in a form of a memory block and which contains, before start of any bus I/O transactions, I/O address decode information for positive claiming of bus transaction ownership, for at least a portion of possible I/O addresses in a system, with said I/O decode map sub-divided in its entirety into a plurality of sub-byte portions, and with each sub-byte portion of said I/O decode map containing positive claiming information for a different one of said at least a portion of said possible I/O addresses in the system; and

using said I/O address decode information for performing address decoding for bus transaction ownership.

23. A method as claimed in claim 22, wherein said I/O decode map more specifically contains decode information for all possible I/O addresses in the system.