Hardware assisted memory backup system and method

• US 6,336,174 B1
• Filed: 08/09/1999
• Issued: 01/01/2002
• Est. Priority Date: 08/09/1999
• Status: Expired due to Term

• Current Assignee: Maxtor Corporation (Seagate Technology Holdings Plc)
• Original Assignee: Maxtor Corporation (Seagate Technology Holdings Plc)
• Inventors: Li, Qiang, Zahornacky, Jon F., Strang, Clifford E. Jr.
• Primary Examiner(s): Yoo, Do Hyun
• Assistant Examiner(s): GOODARZI, NASSER MOAZZAMI
• Application Number:
  US09/370,855
• Time in Patent Office: 876 Days
• Field of Search: 711/162, 711/160, 711/161, 714/6-22, 710/10, 713/340, 370/537, 365/228, 365/229
• US Class Current: 711/162
• CPC Class Codes: G06F 11/1441 Resetting or repowering

Abstract

A hardware assisted memory module (HAMM) is coupled to a conventional computer system. During normal operation of the computer system, the HAMM behaves like a conventional memory module. The HAMM, however, detects and responds to at least one of the following trigger events: 1) power failure, 2) operating system hang-up, or 3) unexpected system reset. Upon detection of a trigger event, the HAMM electronically isolates itself from the host computer system before copying digital information from volatile memory to nonvolatile memory. Once isolated, the HAMM takes its power from an auxiliary power supply. The HAMM can be configured to copy all or part of the digital information to nonvolatile memory. Upon either a request or at power-up, the HAMM copies the digital information from the nonvolatile memory into the volatile memory. If there is a normal computer shutdown, the operating system will first warn the HAMM before shutting down, thus precluding it from performing a backup operation. The operating system determines whether the last shutdown was unexpected by reading a register stored in a reserved area of memory. If the operating system wants the digital information restored, it orders the HAMM to restore the backed-up digital information from nonvolatile memory to volatile memory.

Claims

1. An apparatus coupled to a host computer system for communicating digital information between volatile and nonvolatile memory in response to a trigger event, the apparatus comprising:

a volatile memory coupled to an information source for receiving and storing the digital information;

a nonvolatile memory coupled to the volatile memory for receiving and storing the digital information communicated from the volatile memory; and

a controller coupled to the volatile memory and the nonvolatile memory for controlling the communication of the digital information between the volatile memory and the nonvolatile memory in response to the trigger event, the controller configured to determine the type of the trigger event from control information stored in the volatile memory.

2. The apparatus of claim 1, wherein the volatile memory is DRAM and the nonvolatile memory is flash memory.

3. The apparatus of claim 1, wherein the control information is stored in a portion of memory outside the memory map of the volatile memory.

4. The apparatus of claim 1, wherein the trigger event comprises at least one from the group of trigger events comprising:

unexpected power failure, unexpected system reset, and operating system hang-up.

5. The apparatus of claim 1, further including

isolation devices for electrically isolating the volatile memory, nonvolatile memory and controller from the host computer system in response to the trigger event.

6. The apparatus of claim 5, wherein the isolation devices are CMOS devices.

7. The apparatus of claim 1, further including

an auxiliary power source for providing power to the apparatus in response to the trigger event.

8. The apparatus of claim 7, wherein the auxiliary power source is a battery.

9. The apparatus of claim 8, wherein the battery is recharged by the host computer system during normal operation.

10. The apparatus of claim 1, wherein the control information is provided by the operating system of the host computer system.

11. The apparatus of claim 1, wherein the apparatus couples to the host computer system through a conventional computer memory interface.

12. The apparatus of claim 1, wherein the volatile memory includes a control register for storing the control information.

13. The apparatus of claim 1, the controller further comprising:

a control circuit for generating address and control signals for accessing the volatile and nonvolatile memory;

a power interface circuit coupled to an auxiliary power supply for providing power to the apparatus in response to the trigger event; and

a timing device for determining if the host operating system of the host computer system has hung.

14. The apparatus of claim 13, wherein the timing device is reset by the control information stored in the volatile memory.

15. The apparatus of claim 13, further including a clock generator coupled to the control circuit for providing a clock to the control circuit.

16. The apparatus of claim 1, wherein an image of an operating system kernel is stored in the nonvolatile memory.

17. A memory backup system coupled to a host computer for providing memory backup in response to a trigger event, the system comprising:

a volatile memory coupled to an information source for receiving and storing the digital information;

a nonvolatile memory coupled to the volatile memory for receiving and storing the digital information communicated from the volatile memory;

a controller coupled to the volatile memory and the nonvolatile memory for controlling the communication of the digital information between the volatile memory and the nonvolatile memory in response to the trigger event, the controller configured to determine the type of the trigger event from control information stored in the volatile memory;

isolation devices for electrically isolating the system from the host computer in response to the trigger event; and

an auxiliary power source for providing power to the system in response to the trigger event.

18. The system of claim 17, wherein the trigger event comprises at least one from a group of trigger events comprising:

unexpected power failure, unexpected system reset, and operating system hang-up.

19. The system of claim 17, wherein the control information is provided by the operating system of the host computer.

20. The system of claim 17, wherein the volatile memory includes a control register for storing the control information.

21. The system of claim 17, wherein an image of an operating system kernel is stored in the nonvolatile memory.

22. A memory backup method using a hardware assisted memory module, comprising the steps of:

detecting a trigger event from a host computer system, the host computer system coupled to the hardware assisted memory module;

determining if the trigger event is an unexpected host computer system failure or a normal host computer system shutdown by examining a data structure in volatile memory;

copying digital information from volatile memory to nonvolatile memory if the type of the trigger event is an unexpected host computer system failure; and

storing control information relating to the type of the trigger event in volatile memory.

23. The method of claim 22, further including the steps of:

retrieving the stored control information from volatile memory;

determining from the control information the type of the trigger event; and

copying the digital information from nonvolatile memory to volatile memory if the type of the trigger event was an unexpected system failure.

24. The method of claim 22, further including the steps of:

electrically isolating the hardware assisted memory module from the host computer system; and

coupling the hardware assisted memory module to an auxiliary power source.

25. The method of claim 22, the detecting step including

monitoring the host computer system for power failure.

26. The method of claim 22, the detecting step including

monitoring the host computer system for a system reset.

27. The method of claim 22, detecting step including monitoring the host computer system for an operating system hang-up.

28. The method of claim 27, the monitoring step including the steps of:

setting a watchdog timer; and

performing the storing step if the watchdog timer exceeds a predetermined time limit.

29. The method of claim 22, the storing step further including the steps of:

providing a unique address sequence for accessing a portion of reserved volatile memory for storing the control information.

30. The method of claim 22, further including the step of:

copying an operating system kernel from nonvolatile memory to volatile memory.

31. A computer-readable medium in a hardware assisted memory module containing instructions thereon, which, when executed by a processor, perform the steps of:

detecting a trigger event from a host computer system, the host computer system coupled to the hardware assisted memory module;

determining if the trigger event is an unexpected host computer system failure or a normal host computer system shutdown by examining a data structure in volatile memory;

copying digital information from volatile memory to nonvolatile memory if the type of the trigger event is an unexpected host computer system failure; and

storing control information relating to the type of the trigger event in volatile memory.

32. The computer-readable medium of claim 31, wherein the instructions further comprise:

retrieving the stored control information from volatile memory;

determining from the control information the type of the trigger event; and

copying the digital information from nonvolatile memory to volatile memory if the type of the trigger event was an unexpected system failure.

33. The computer-readable medium of claim 31, wherein the instructions further comprise:

electrically isolating the hardware assisted memory module from the host computer system; and

coupling the hardware assisted memory module to an auxiliary power source.

34. The computer-readable medium of claim 31, wherein the instructions further comprise:

monitoring the host computer system for power failure.

35. The computer-readable medium of claim 31, wherein the instructions further comprise:

monitoring the host computer system for a system reset.

36. The computer-readable medium of claim 31, wherein the instructions further comprise:

monitoring the host computer system for an operating system hang-up.

37. The computer-readable medium of claim 31, wherein the instructions further comprise:

setting a watchdog timer; and

performing the storing step if the watchdog timer exceeds a predetermined time limit.

38. The computer-readable medium of claim 31, where the instructions further comprise:

providing a unique address sequence for accessing a portion of reserved volatile memory for storing the control information.

39. The computer-readable medium of claim 31, wherein the instructions further comprise:

copying an operating system kernel from nonvolatile memory to volatile memory.

40. A computer-readable medium in a hardware assisted memory module containing instructions thereon, which, when executed by a processor, perform the steps of:

detecting a trigger event from a host computer system, the host computer system coupled to the hardware assisted memory module;

determining if the trigger event is an unexpected host computer system failure or a normal host computer system shutdown by examining a data structure in volatile memory;

storing control information relating to the type of the trigger event in volatile memory;

electrically isolating the hardware assisted memory module from the host computer system;

coupling the hardware assisted memory module to an auxiliary power source; and

copying digital information from volatile memory to nonvolatile memory if the type of the trigger event is an unexpected host computer system failure.

41. A memory backup system, comprising:

a volatile memory for receiving and storing digital information from an information source;

a nonvolatile memory for receiving and storing the digital information communicated from the volatile memory;

a control register for storing control information that indicates the nature and occurrence of a trigger event; and

a controller for transferring the digital information between the volatile memory and the nonvolatile memory in response to the control information indicating that the trigger event has occurred.

42. The system of claim 41, wherein the trigger event is a power failure.

43. The system of claim 41, wherein the trigger event is a system reset.

44. The system of claim 41, wherein the trigger event is an operating system hang-up.

45. The system of claim 41, wherein the control information further indicates the nature and occurrence of a second trigger event and a third trigger event, and the controller transfers the digital information between the volatile memory and the nonvolatile memory in response to the control information indicating that any of the trigger events has occurred.

46. The system of claim 45, wherein the trigger event is a power failure, the second trigger event is a system reset and the third trigger event is an operating system hang-up.

47. The system of claim 41, wherein the system includes isolation devices, and the controller instructs the isolation devices to electrically isolate the system from the information source in response to the control information indicating that the trigger event has occurred.

48. The system of claim 41, wherein the system is adapted to be directly connected to a system memory bus that is directly connected to a central processing unit.

49. The system of claim 41, wherein the control register is within the volatile memory and outside a memory map of the volatile memory.

50. The system of claim 41, wherein the controller transfers the digital information between the volatile memory and the nonvolatile memory when the trigger event is unexpected by an operating system, and the controller alters the control information to indicate the absence of the trigger event in response to the operating system indicating that the trigger event is expected.

51. A memory backup system, comprising:

a volatile memory for receiving and storing digital information from an information source;

a nonvolatile memory for receiving and storing the digital information communicated from the volatile memory; and

a controller for (1) examining a data structure in the volatile memory to determine whether a trigger event is expected or unexpected by an operating system, (2) transferring the digital information between the volatile memory and the nonvolatile memory if the trigger event is unexpected by the operating system, and (3) not transferring the digital information between the volatile memory and the nonvolatile memory if the trigger event is expected by the operating system.

52. The system of claim 51, wherein the controller includes a volatile memory controller coupled to the volatile memory and a nonvolatile memory controller coupled to the nonvolatile memory.

53. The system of claim 52, wherein the controller includes an address counter coupled to the volatile memory controller and the nonvolatile memory controller.

54. The system of claim 53, wherein the controller includes a microsequencer coupled to the volatile memory controller, the nonvolatile memory controller and the address counter.

55. The system of claim 51, wherein the controller includes a voltage monitor that indicates a system power supply failure when a system power supply falls below a reference voltage level, a timer that indicates the operating system is hung when the operating system fails to reset the timer, and a system reset line that indicates when a system reset is activated.

56. The system of claim 55 wherein the controller includes an OR gate with separate inputs coupled to outputs of the voltage monitor, the timer and the system reset line.

57. The system of claim 56, wherein the controller includes a normal shutdown sequencer that indicates a normal system shutdown.

58. The system of claim 57, wherein the controller includes an AND gate with separate inputs coupled to outputs of the OR gate and the normal shutdown sequencer.

59. The system of claim 51, wherein the data structure also indicates the nature of the trigger event.

60. The system of claim 51, wherein the system is adapted to be directly connected to a system memory bus that is directly connected to a central processing unit.

61. A memory backup system, comprising:

a volatile memory for receiving and storing digital information from an information source;

a nonvolatile memory for receiving and storing the digital information communicated from the volatile memory;

a control register for storing control information that indicates the occurrence of first and second trigger events; and

a controller for transferring the digital information between the volatile memory and the nonvolatile memory in response to the control information indicating that any of the trigger events has occurred.

62. The system of claim 61, wherein the trigger events are selected from the group consisting of a power failure, a system reset and an operating system hang-up.

63. The system of claim 61, wherein the first trigger event is a power failure, and the second trigger event is selected from the group consisting of a system reset and an operating system hang-up.

64. The system of claim 61, wherein the first trigger event is a system reset.

65. The system of claim 61, wherein the first trigger event is an operating system hang-up.

66. The system of claim 61, wherein the control information further indicates the nature of the trigger events.

67. The system of claim 61, wherein the system includes isolation devices, and the controller instructs the isolation devices to electrically isolate the system from the information source in response to the control information indicating that any of the trigger events has occurred.

68. The system of claim 61, wherein the system is adapted to be directly connected to a system memory bus that is directly connected to a central processing unit.

69. The system of claim 61, wherein the control register is within a reserved portion of the volatile memory and outside a memory map of the volatile memory.

70. The system of claim 61, wherein the controller transfers the digital information between the volatile memory and the nonvolatile memory when the first trigger event has occurred and is unexpected by an operating system, and the controller alters the control information to indicate the absence of the first trigger event in response to the operating system indicating that the first trigger event is expected.

71. A memory backup system, comprising:

a volatile memory for receiving and storing digital information from an information source;

a nonvolatile memory for receiving and storing the digital information communicated from the volatile memory;

a control register for storing control information that indicates the occurrence of first and second trigger events, wherein the control register is within the volatile memory; and

a controller for transferring the digital information between the volatile memory and the nonvolatile memory in response to the control information indicating that any of the trigger events has occurred.

72. The system of claim 71, wherein the trigger events are selected from the group consisting of a power failure, a system reset and an operating system hang-up.

73. The system of claim 71, wherein the first trigger event is a power failure, and the second trigger event is selected from the group consisting of a system reset and an operating system hang-up.

74. The system of claim 71, wherein the first trigger event is a system reset.

75. The system of claim 71, wherein the first trigger event is an operating system hang-up.

76. The system of claim 71, wherein the control information further indicates the nature of the trigger events.

77. The system of claim 71, wherein the system includes isolation devices, and the controller instructs the isolation devices to electrically isolate the system from the information source in response to the control information indicating that any of the trigger events has occurred.

78. The system of claim 71, wherein the system is adapted to be directly connected to a system memory bus that is directly connected to a central processing unit.

79. The system of claim 71, wherein the control register is within a reserved portion of the volatile memory and outside a memory map of the volatile memory.

80. The system of claim 71, wherein the controller transfers the digital information between the volatile memory and the nonvolatile memory when the first trigger event has occurred and is unexpected by an operating system, and the controller alters the control information to indicate the absence of the first trigger event in response to the operating system indicating that the first trigger event is expected.