RISC86 instruction set

• US 6,336,178 B1
• Filed: 09/11/1998
• Issued: 01/01/2002
• Est. Priority Date: 10/06/1995
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Favor, John G.
• Primary Examiner(s): Donaghue, Larry D.
• Application Number:
  US09/152,043
• Time in Patent Office: 1,208 Days
• Field of Search: 712/23, 712/205, 712/208, 712/209, 712/210, 712/215, 712/212, 712/21.T, 712/213, 717/5
• US Class Current: 712/23
• CPC Class Codes: G06F 7/74 Selecting or encoding within a word the position of one or more bits having a specified value, e.g. most or least significant one or zero detection, priority encoders with shifting G06F5/01
• CPC Class Codes: G06F 9/30152 Determining start or end of instruction; determining instruction length
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/3017 Runtime instruction translation, e.g. macros
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/30185 according to one or more bits in the instruction, e.g. prefix, sub-opcode
• CPC Class Codes: G06F 9/324 using program counter relative addressing
• CPC Class Codes: G06F 9/3806 using address prediction, e.g. return stack, branch history buffer
• CPC Class Codes: G06F 9/3812 with instruction modification, e.g. store into instruction stream
• CPC Class Codes: G06F 9/3816 Instruction alignment, e.g. cache line crossing
• CPC Class Codes: G06F 9/382 Pipelined decoding, e.g. using predecoding
• CPC Class Codes: G06F 9/3822 Parallel decoding, e.g. parallel decode units
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3853 of compound instructions
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/45533 Hypervisors; Virtual machine monitors
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

An internal RISC-type instruction structure furnishes a fixed bit-length template including a plurality of defined bit fields for a plurality of operation (Op) formats. One format includes an instruction-type bit field, two source-operand bit fields and one destination-operand bit field for designating a register-to-register operation. Another format is a load-store format that includes an instruction-type bit field, an identifier of a source or destination register for the respective load or store operation, and bit fields for specifying the segment, base and index parameters of an address.

Claims

1. A microprocessor comprising:

a source of CISC-like instructions;

a RISC-like processor core for executing a plurality of RISC-like operations in parallel; and

a decoder coupling the source of CISC-like instructions to the RISC-like processor core, the decoder for converting CISC-like instructions into operations of a RISC-like instruction set including;

a plurality of mutually-uniform bit-length instruction codes, each code being divided into a plurality of defined-usage bit fields and the codes being classified into a plurality of instruction classes, the code in an instruction class having a mutually-consistent definition of defined-usage bit-fields including a bit-field that is mapped using indirect specifiers so that a single mutually-uniform bit-length instruction code maps into a plurality of instruction versions, wherein the instruction classes include;

a register operation (RegOp) class including arithmetic operations, shift operations and move operations and having defined-usage bit-fields including an operation type field, three operand bit-fields for designating a first source operand, a second source operand and a destination operand, a bit-field for designating a data size of the operands, wherein the RegOp class further includes special register read and write operations and has defined-usage bit-fields including;

an extension bit-field for specifying a condition code for a conditional move instruction and for specifying a special register to be read and written by the special register read and write operations.

2. The microprocessor according to claim 1, wherein the RegOp class further includes an operation that modifies one or more status flags, the RegOp class further having defined-usage bit-fields including:

an extension bit-field for specifying the one or more status flags that are modified by the operation; and

a set status bit-field for causing the operation to modify status flags in accordance with the extension bit-field.

3. The microprocessor according to claim 1, wherein the RegOp class of operations includes an operation for writing a program counter to redirect processor execution.

4. A microprocessor comprising:

a source of CISC-like instructions;

a RISC-like processor core for executing a plurality of RISC-like operations in parallel; and

a decoder coupling the source of CISC-like instructions to the RISC-like processor core, the decoder for converting CISC-like instructions into operations of a RISC-like instruction set including;

a plurality of mutually-uniform bit-length instruction codes, each code being divided into a plurality of defined-usage bit fields and the codes being classified into a plurality of instruction classes, the code in an instruction class having a mutually-consistent definition of defined-usage bit-fields including a bit-field that is mapped using indirect specifiers so that a single mutually-uniform bit-length instruction code maps into a plurality of instruction versions, wherein the instruction classes include;

a register operation (RegOp) class including arithmetic operations, shift operations and move operations and having defined-usage bit-fields including an operation type field, three operand bit-fields for designating a first source operand, a second source operand and a destination operand, a bit-field for designating a data size of the operands, wherein the RegOp class further has defined-usage bit-fields including;

a bit-field for designating an execution unit for executing an operation.

5. The microprocessor according to claim 4, wherein the RegOp class further includes an operation that modifies one or more status flags, the RegOp class further having defined-usage bit-fields including:

an extension bit-field for specifying the one or more status flags that are modified by the operation; and

a set status bit-field for causing the operation to modify status flags in accordance with the extension bit-field.

6. The microprocessor according to claim 4, wherein the RegOp class of operations includes an operation for writing a program counter to redirect processor execution.

7. A microprocessor comprising:

a source of CISC-like instructions;

a RISC-like processor core for executing a plurality of RISC-like operations in parallel; and

a decoder coupling the source of CISC-like instructions to the RISC-like processor core, the decoder for converting CISC-like instructions into operations of a RISC-like instruction set including;

a plurality of mutually-uniform bit-length instruction codes, each code being divided into a plurality of defined-usage bit fields and the codes being classified into a plurality of instruction classes, the code in an instruction class having a mutually-consistent definition of defined-usage bit-fields including a bit-field that is mapped using indirect specifiers so that a single mutually-uniform bit-length instruction code maps into a plurality of instruction versions, wherein the instruction classes include;

a register operation (RegOp) class including arithmetic operations, shift operations and move operations and having defined-usage bit-fields including an operation type field, three operand bit-fields for designating a first source operand, a second source operand and a destination operand, a bit-field for designating a data size of the operands, wherein the RegOp class of operations includes a check selector operation for simultaneously checking a memory segment selector for access permission and loading the selector if permission is attained.

8. The microprocessor according to claim 7, wherein the RegOp class further includes an operation that modifies one or more status flags, the RegOp class further having defined-usage bit-fields including:

an extension bit-field for specifying the one or more status flags that are modified by the operation; and

a set status bit-field for causing the operation to modify status flags in accordance with the extension bit-field.

9. The microprocessor according to claim 7, wherein the RegOp class of operations includes an operation for writing a program counter to redirect processor execution.

10. A microprocessor comprising:

a source of CISC-like instructions;

a RISC-like processor core for executing a plurality of RISC-like operations in parallel; and

a decoder coupling the source of CISC-like instructions to the RISC-like processor core, the decoder for converting CISC-like instructions into operations of a RISC-like instruction set including;

a plurality of mutually-uniform bit-length instruction codes, each code being divided into a plurality of defined-usage bit fields and the codes being classified into a plurality of instruction classes, the code in an instruction class having a mutually-consistent definition of defined-usage bit-fields including a bit-field that is mapped using indirect specifiers so that a single mutually-uniform bit-length instruction code maps into a plurality of instruction versions, wherein the instruction classes include;

a register operation (RegOp) class including arithmetic operations, shift operations and move operations and having defined-usage bit-fields including an operation type field, three operand bit-fields for designating a first source operand, a second source operand and a destination operand, a bit-field for designating a data size of the operands, wherein the RegOp class of operations includes a check selector operation (CHKS) for simultaneously checking a memory segment selector for access permission and loading the selector if permission is attained.

11. The microprocessor according to claim 10, wherein the RegOp class further includes an operation that modifies one or more status flags, the RegOp class further having defined-usage bit-fields including:

an extension bit-field for specifying the one or more status flags that are modified by the operation; and

a set status bit-field for causing the operation to modify status flags in accordance with the extension bit-field.

12. The microprocessor according to claim 10, wherein the RegOp class of operations includes an operation for writing a program counter to redirect processor execution.

13. A microprocessor comprising:

a source of CISC-like instructions;

a RISC-like processor core for executing a plurality of RISC-like operations in parallel; and

a decoder coupling the source of CISC-like instructions to the RISC-like processor core, the decoder for converting CISC-like instructions into operations of a RISC-like instruction set including;

a plurality of mutually-uniform bit-length instruction codes, each code being divided into a plurality of defined-usage bit fields and the codes being classified into a plurality of instruction classes, the code in an instruction class having a mutually-consistent definition of defined-usage bit-fields including a bit-field that is mapped using indirect specifiers so that a single mutually-uniform bit-length instruction code maps into a plurality of instruction versions, wherein the instruction classes include;

a register operation (RegOp) class including arithmetic operations, shift operations and move operations and having defined-usage bit-fields including an operation type field, three operand bit-fields for designating a first source operand, a second source operand and a destination operand, a bit-field for designating a data size of the operands, wherein the RegOp class of operations includes;

a write descriptor real (WRDR) operation for loading a segment register in a real mode fashion;

a write descriptor protected mode high (WRDH) operation and a write descriptor protected mode low (WRDL) operation for performing a sequence of checking operations for checking data segments and I/O address space as an emulation code sequence of hardware primitives.

14. The microprocessor according to claim 13, wherein the RegOp class further includes an operation that modifies one or more status flags, the RegOp class further having defined-usage bit-fields including:

an extension bit-field for specifying the one or more status flags that are modified by the operation; and

a set status bit-field for causing the operation to modify status flags in accordance with the extension bit-field.

15. The microprocessor according to claim 13, wherein the RegOp class of operations includes an operation for writing a program counter to redirect processor execution.

16. A microprocessor comprising:

a source of CISC-like instructions;

a RISC-like processor core for executing a plurality of RISC-like operations in parallel; and

a decoder coupling the source of CISC-like instructions to the RISC-like processor core, the decoder for converting CISC-like instructions into operations of a RISC-like instruction set including;

a plurality of mutually-uniform bit-length instruction codes, each code being divided into a plurality of defined-usage bit fields and the codes being classified into a plurality of instruction classes, the code in an instruction class having a mutually-consistent definition of defined-usage bit-fields including a bit-field that is mapped using indirect specifiers so that a single mutually-uniform bit-length instruction code maps into a plurality of instruction versions, wherein the indirect specifiers specify an instruction parameter selected from the parameters including an operating register, a data size and an address size.

17. The microprocessor according to claim 16, wherein the instruction classes include:

a load operation (LdOp) class including load operations and having defined-usage bit-fields including an operation type field, a plurality of bit-fields for designating a source address in memory, a bit-field for designating a destination register for receiving data from the source address in memory, and a bit-field for designating a data size of the source-destination data.

18. The microprocessor according to claim 16, wherein the instruction classes include:

a store operation (StOp) class including store operations having defined-usage bit-fields including an operation type field, a plurality of bit-fields for designating a store address in memory, a bit-field for designating a data source register for sourcing data from the store register, and a bit-field for designating a data size of the source-destination data.

19. The microprocessor according to claim 16, wherein the instruction classes further include a load immediate operation class (LIMMOp) having defined-usage bit-fields including:

an immediate data high (ImmHi) bit-field and an immediate data low (ImmLo) bit-field for designating the immediate data value; and

a bit-field for designating a data destination register for receiving data from the load-store address in memory.

20. The microprocessor according to claim 16, wherein the instruction classes further include a special operation class (SpecOp) including a conditional branch operation, a set default fault handler address operation, a set alternate fault handler address operation and an unconditional fault operation and having defined-usage bit-fields including:

a bit-field for designating a condition code; and

a data immediate bit-field for designating a signed immediate data value.

21. A microprocessor comprising:

a source of CISC-like instructions;

a RISC-like processor core for executing a plurality of RISC-like operations in parallel; and

a decoder coupling the source of CISC-like instructions to the RISC-like processor core, the decoder for converting CISC-like instructions into operations of a RISC-like instruction set including;

a plurality of mutually-uniform bit-length instruction codes, each code being divided into a plurality of defined-usage bit fields and the codes being classified into a plurality of instruction classes, the code in an instruction class having a mutually-consistent definition of defined-usage bit-fields including a bit-field that is mapped using indirect specifiers so that a single mutually-uniform bit-length instruction code maps into a plurality of instruction versions, wherein the instruction classes include;

a load-store operation (LdStOp) class including load and store operations and having defined-usage bit-fields including an operation type field, a plurality of bit-fields for designating a load-store address in memory, a bit-field for designating a data source-destination register for sourcing-receiving data from the load-store address in memory, and a bit-field for designating a data size of the source-destination data, wherein the plurality of bit-fields for designating a load-store address in memory in the LdStOp class includes;

a segment register for designating a memory segment of the load-store address;

a base register for designating a base of the load-store memory address;

an index register for designating a memory index; and

an index scale factor bit-field for designating an index scale factor.

22. The microprocessor according to claim 21, wherein the LdStOp class of operations includes a check data effective address (CDA) operation.

23. The microprocessor according to claim 21, wherein the LdStOp class of operations includes a check instruction effective address (CIA) operation.

24. The microprocessor according to claim 21, wherein the LdStOp class of operations includes a store integer data with base register update (STUPD) operation.

25. The microprocessor according to claim 21, wherein the LdStOp class of operations includes an operation for invalidating a TLB address (TIA).

26. A superscalar microprocessor comprising:

a source of CISC-like instructions;

a RISC-like processor core for executing a plurality of RISC-like operations in parallel; and

a decoder coupling the source of CISC-like instructions to the RISC-like processor core, the decoder for converting CISC-like instructions into operations of a RISC-like instruction set including;

a plurality of mutually-uniform bit-length instruction codes, each code being divided into a plurality of defined-usage bit fields and the codes being classified into a plurality of instruction classes, each code in an instruction class having a mutually-consistent definition of defined-usage bit-fields, the instruction classes including;

a register operation (RegOp) class including arithmetic operations, shift operations and move operations and having defined-usage bit-fields including an operation type field, three operand bit-fields for designating a first source operand, a second source operand and a destination operand, a bit-field for designating a data size of the operands;

a load-store operation (LdStOp) class including load and store operations and having defined-usage bit-fields including an operation type field, a plurality of bit-fields for designating a load-store address in memory, a bit-field for designating a data source-destination register for sourcing-receiving data from the load-store address in memory, and a bit-field for designating a data size of the source-destination data; and

a load immediate operation class (L,IMMOp) having defined-usage bit-fields including;

an immediate data high (ImmHi) bit-field and an immediate data low (ImmLo) bit-field for designating the immediate data value; and

a bit-field for designating a data destination register for receiving data from the load-store address in memory.

27. A microprocessor according to claim 26, wherein the instruction set RegOp class further includes an operation that modifies one or more status flags, the RegOp class further having defined-usage bit-fields including:

an extension bit-field for specifying the one or more status flags that are modified by the operation; and

a set status bit-field for causing the operation to modify status flags in accordance with the extension bit-field.

28. A superscalar microprocessor comprising:

a source of CISC-like instructions;

a RISC-like processor core for executing a plurality of RISC-like operations in parallel; and

a decoder coupling the source of CISC-like instructions to the RISC-like processor core, the decoder for converting CISC-like instructions into operations of a RISC-like instruction set including;

a plurality of mutually-uniform bit-length instruction codes, each code being divided into a plurality of defined-usage bit fields and the codes being classified into a plurality of instruction classes, each code in an instruction class having a mutually-consistent definition of defined-usage bit-fields, the instruction classes including;

a register operation (RegOp) class including arithmetic operations, shift operations and move operations and having defined-usage bit-fields including an operation type field, three operand bit-fields for designating a first source operand, a second source operand and a destination operand, a bit-field for designating a data size of the operands;

a load-store operation (LdStOp) class including load and store operations and having defined-usage bit-fields including an operation type field, a plurality of bit-fields for designating a load-store address in memory, a bit-field for designating a data source-destination register for sourcing-receiving data from the load-store address in memory, and a bit-field for designating a data size of the source-destination data; and

a special operation class (SpecOp) including a conditional branch operation, a set default fault handler address operation, a set alternate fault handler address operation and an unconditional fault operation and having defined-usage bit-fields including;

a bit-field for designating a condition code; and

a data immediate bit-field for designating a signed immediate data value.

29. A microprocessor according to claim 28, wherein the instruction set RegOp class further includes an operation that modifies one or more status flags, the RegOp class further having defined-usage bit-fields including:

an extension bit-field for specifying the one or more status flags that are modified by the operation; and

a set status bit-field for causing the operation to modify status flags in accordance with the extension bit-field.

30. A computer system comprising:

a memory subsystem which stores data and instructions; and

a processor operably coupled to access the data and instructions stored in the memory subsystem, wherein the processor includes;

a source of CISC-like instructions;

a RISC-like processor core for executing a plurality of RISC-like operations in parallel; and

a decoder coupling the source of CISC-like instructions to the RISC-like processor core, the decoder for converting CISC-like instructions into operations of a RISC-like instruction set including;

a plurality of mutually-uniform bit-length instruction codes, each code being divided into a plurality of defined-usage bit fields and the codes being classified into a plurality of instruction classes, each code in an instruction class having a mutually-consistent definition of defined-usage bit-fields, the instruction classes including;

a register operation (RegOp) class including arithmetic operations, shift operations and move operations and having defined-usage bit-fields including an operation type field, three operand bit-fields for designating a first source operand, a second source operand and a destination operand, a bit-field for designating a data size of the operands;

a load-store operation (LdStOp) class including load and store operations and having defined-usage bit-fields including an operation type field, a plurality of bit-fields for designating a load-store address in memory, a bit-field for designating a data source-destination register for sourcing-receiving data from the load-store address in memory, and a bit-field for designating a data size of the source-destination data, and

at least one of a load immediate operation class (LIMMOp) and a special operation class (SpecOp), wherein the LIMMOp class has defined-usage bit-fields including;

an immediate data high (ImmHi) bit-field and an immediate data low (ImmLo) bit-field for designating the immediate data value; and

a bit-field for designating a data destination register for receiving data from the load-store address in memory; and

wherein the SpecOp class includes a conditional branch operation, a set default fault handler address operation, a set alternate fault handler address operation and an unconditional fault operation and having defined-usage bit-fields including;

a bit-field for designating a condition code; and

a data immediate bit-field for designating a signed immediate data value.

31. The computer system of claim 30, wherein the processor and the memory subsystem are components of a motherboard.

32. The computer system of claim 31, wherein the motherboard further comprises a backplane bus operably connected to the processor, and wherein the computer system further comprises one or more devices on cards connected to the motherboard via the backplane bus.

33. The computer system of claim 30, further comprising a parallel device interface operably coupled to the processor.

34. The computer system of claim 33, further comprising a printer connected to the processor via the parallel interface.

35. The computer system of claim 30, further comprising a serial device interface operably coupled to the processor.

36. The computer system of claim 35, further comprising a modem connected to the processor via the serial interface.

37. The computer system of claim 30, further comprising a graphics adapter operably coupled to the processor.

38. The computer system of claim 37, further comprising a video display connected to the processor via the graphics adapter.

39. The computer system of claim 30, further comprising a local area network adapter operably coupled to the processor.

40. The computer system of claim 39, further comprising a network of devices connected to the processor via the network adapter.

41. The computer system of claim 30, further comprising a disk controller operably coupled to the processor.

42. The computer system of claim 41, further comprising a hard disk connected to the processor via the disk controller.

43. The computer system of claim 41, further comprising a floppy disk connected to the processor via the disk controller.

44. A microprocessor comprising:

a source of CISC-like instructions;

a RISC-like processor core for executing a plurality of RISC-like operations in parallel; and

a decoder coupling the source of CISC-like instructions to the RISC-like processor core, the decoder for converting CISC-like instructions into operations of a RISC-like instruction set including;

a plurality of mutually-uniform bit-length instruction codes, each code being divided into a plurality of defined-usage bit fields and the codes being classified into a plurality of instruction classes, the code in an instruction class having a mutually-consistent definition of defined-usage bit-fields including a bit-field that is mapped using indirect specifiers so that a single mutually-uniform bit-length instruction code maps into a plurality of instruction versions, wherein the instruction classes include;

a special operation class (SpecOp) including a conditional branch operation, a set default fault handler address operation, a set alternate fault handler address operation and an unconditional fault operation and having defined-usage bit-fields including;

a bit-field for designating a condition code; and

a data immediate bit-field for designating a signed immediate data value, wherein the SpecOp class of operations includes an operation for loading a constant (LDK).

45. The microprocessor according to claim 44, wherein the special operation class (SpecOp) further includes a load constant operation and the defined-usage bit-fields further include:

a bit-field for designating a data destination register; and

a bit-field for designating a data size of constant data.

46. A microprocessor comprising:

a source of CISC-like instructions;

a RISC-like processor core for executing a plurality of RISC-like operations in parallel; and

a decoder coupling the source of CISC-like instructions to the RISC-like processor core, the decoder for converting CISC-like instructions into operations of a RISC-like instruction set including;

a plurality of mutually-uniform bit-length instruction codes, each code being divided into a plurality of defined-usage bit fields and the codes being classified into a plurality of instruction classes, the code in an instruction class having a mutually-consistent definition of defined-usage bit-fields including a bit-field that is mapped using indirect specifiers so that a single mutually-uniform bit-length instruction code maps into a plurality of instruction versions, wherein the instruction classes include;

a special operation class (SpecOp) including a conditional branch operation, a set default fault handler address operation, a set alternate fault handler address operation and an unconditional fault operation and having defined-usage bit-fields including;

a bit-field for designating a condition code; and

a data immediate bit-field for designating a signed immediate data value, wherein the SpecOp class of operations includes a load constant data (LDKD) operation.

48. The microprocessor according to claim 46, wherein the special operation class (SpecOp) further includes a load constant operation and the defined-usage bit-fields further include:

a bit-field for designating a data destination register; and

a bit-field for designating a data size of constant data.

47. A microprocessor comprising:

a source of CISC-like instructions;

a RISC-like processor core for executing a plurality of RISC-like operations in parallel; and

a decoder coupling the source of CISC-like instructions to the RISC-like processor core, the decoder for converting CISC-like instructions into operations of a RISC-like instruction set including;

a plurality of mutually-uniform bit-length instruction codes, each code being divided into a plurality of defined-usage bit fields and the codes being classified into a plurality of instruction classes, the code in an instruction class having a mutually-consistent definition of defined-usage bit-fields including a bit-field that is mapped using indirect specifiers so that a single mutually-uniform bit-length instruction code maps into a plurality of instruction versions, wherein a defined-usage bit-field of an operation is designated by a substituted value that is determined by an emulation environment of the processor.