Error correction coding and decoding method, and circuit using said method

• US 6,336,203 B1
• Filed: 03/26/1998
• Issued: 01/01/2002
• Est. Priority Date: 05/30/1995
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation), Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Yoshida, Hideo
• Primary Examiner(s): Chung, Phung M.
• Application Number:
  US09/048,563
• Time in Patent Office: 1,377 Days
• Field of Search: 714/785, 714/746, 714/752, 714/755, 714/763
• US Class Current: 714/785
• CPC Class Codes: H03M 13/15 Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes H03M13/17 takes precedence
• CPC Class Codes: H03M 13/151 using error location or error correction polynomials
• CPC Class Codes: H03M 13/47 Error detection, forward error correction or error protection, not provided for in groups H03M13/01 - H03M13/37

Abstract

In the coding and decoding of Reed-Solomon codes formed of symbols larger than information symbols, redundant circuitry is eliminated, error detection and correction are preformed using a simple construction, and the reliability of error detection and correction is improved by processing only data of the same size as the information symbols. Two bits of dummy data which are surplus bits in 10 bits of one symbol of information are supplied from a dummy data input circuit to 8 bit input data. At the same time, syndrome data is generated form the surplus parts of check symbols by a syndrome data correction circuit. A part of the 10 bit data is selected by a selector, and supplied to a Galois field summation circuit. The output of the Galois field summation circuit is output to a register, and the output of this register is either selected without modification or via a Galois field coefficient multiplying circuit by a selector, and supplied to the Galois field summation circuit. The output of the register is output as syndrome data by a syndrome output terminal.

Claims

1. An error correction decoding circuit which stores received, coded error correction data from a data input part in a data buffer memory, and performs a plurality of decoding operations according to said error correction data, said circuit comprising:

first syndrome calculating means for calculating a syndrome of received data input by said data input part,

second syndrome calculating means for calculating a syndrome of data stored in said data buffer memory,

decoding means for decoding received data based on the two syndromes calculated by said first and second syndrome calculating means, and

correcting means for performing error correction,

said decoding means comprising selecting decoding means for selecting either one of said two syndromes and decoding it.

2. The error correction decoding circuit according to claim 1, wherein

said decoding means comprises an error detection means receiving said first and second syndromes from said selector on a time division basis.

3. The error correcting decoder according to claim 2, wherein

said error detecting means detects an error position and an error magnitude.

4. The error correcting decoder according to claim 3, wherein

said first syndrome calculating means receives said first data parallel to said data buffer memory.

5. The error correcting decoder according to claim 4, wherein

said second syndrome calculating means skips calculating a syndrome for data which is calculated by said first syndrome calculating means.

6. An error correcting decoder, comprising:

a first syndrome calculating circuit calculating a first syndrome of first data from a data line;

a buffer memory storing second data from said data line;

a second syndrome calculating circuit calculating a second syndrome of said second data from said buffer memory;

an error detection circuit detecting errors according to said first or second syndromes; and

an error correcting circuit correcting said errors detected by said error detection circuit.

7. The error correcting decoder according to claim 6, further comprising:

a selector circuit selects either said first or second syndrome, wherein said error detection circuit receives said first and second syndromes from said selector on a time division basis.

8. Th error correcting decoder according to claim 7, wherein

said error detecting circuit detects an error position and an error magnitude.

9. The error correcting decoder according to claim 6, wherein

said first syndrome calculating circuit receives said first data parallel to said buffer memory.

10. The error correcting decoder according to claim 6, wherein

said buffer memory is a DRAM.

11. The error correcting decoder according to claim 6, wherein

said second syndrome calculating circuit skips calculating a syndrome for said first data.

12. A correction decoding circuit comprising:

a first syndrome calculating circuit calculating a first syndrome of first data from a data input part;

a second syndrome calculating circuit calculating a second syndrome of a second data stored in a buffer memory connecting to said data input part;

an error detection circuit detecting errors according to said first and second syndromes; and

an error correcting circuit correcting said errors detected by said error detection circuit.