Multichip semiconductor device

• US 6,337,579 B1
• Filed: 03/02/2000
• Issued: 01/08/2002
• Est. Priority Date: 03/05/1999
• Status: Expired due to Term

• Current Assignee: Achlys Technologies Inc.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Mochida, Hiroo
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): PAIK, STEVEN SANGYUL
• Application Number:
  US09/517,283
• Time in Patent Office: 677 Days
• Field of Search: 326/38, 326/40, 326/41, 326/101
• US Class Current: 326/41
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01077 Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A multichip semiconductor device has a first semiconductor chip and a second semiconductor chip superposed on and bonded to each other so as to form a chip-on-chip structure. The first semiconductor chip has a field-programmable gate array circuit and a switch circuit formed thereon. The second semiconductor chip has a non-volatile configuration memory circuit formed thereon for storing the setting information about how to set the circuit of the field-programmable gate array circuit.

Claims

1. A multichip semiconductor device, comprising:

a first semiconductor chip having a field-programmable gate array circuit portion;

a second semiconductor chip having a programmable non-volatile memory for storing setting information about how to set a circuit of the field-programmable gate array circuit portion;

an external connection terminal formed on the first semiconductor chip;

a switch circuit formed on the first semiconductor chip and connected to the external connection terminal;

an input/output line for connecting the switch circuit and the field-programmable gate array circuit portion to each other;

a first connecting member for connecting the field-programmable gate array circuit portion and the non-volatile memory to each other;

a second connecting member for connecting the switch circuit and the non-volatile memory to each other; and

a setting information protecting mechanism for switching the switch circuit to the second state so as to disconnect the external connection terminal from the non-volatile memory permanently after the setting information has been stored in the non-volatile memory by being fed thereto from the external connection terminal through the switch circuit and the second connecting member,

wherein the switch circuit can be switched between a first state connected to the second connecting member and a second state connected to the field-programmable gate array circuit portion, and the setting information about how to set the circuit of the field-programmable gate array circuit portion is written to the non-volatile memory by way of the second connecting member when the switch circuit is in the first state.

2. A multichip semiconductor device as claimed in claim 1,

wherein the first and second semiconductor chips are bonded together by superposing the second semiconductor chip on and bonding it to a surface of the first semiconductor chip so as to form a chip-on-chip structure as a whole.