Phase-lock loop with independent phase and frequency adjustments

• US 6,337,589 B1
• Filed: 08/07/1998
• Issued: 01/08/2002
• Est. Priority Date: 09/11/1997
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Ooishi, Tsukasa
• Primary Examiner(s): Lam, Tuan T.
• Application Number:
  US09/130,606
• Time in Patent Office: 1,250 Days
• Field of Search: 331/10, 331/11, 331/15, 331/17, 331/25, 327/147, 327/148, 327/150, 327/151, 327/156, 327/157, 327/159, 327/160
• US Class Current: 327/156
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/113 using frequency discriminator

Abstract

A PLL is provided with separate phase and frequency adjustment circuits to adjust the frequency of a produced internal clock independently from adjusting its phase. The phase adjustment circuit determines a phase error between the internal clock and an external clock, and averages the phase error over a predetermined time period to produce the corresponding control current. The frequency adjustment circuit detects the difference between the frequency of the internal clock and the frequency of the external clock to determine a frequency error. An accumulator accumulates the frequency error during the predetermined time period to produce the corresponding control current. Based on values of the control currents produced by the phase and frequency adjustment circuits, a current calculator calculates a resulting value of the control current to be applied to a CCO to modify its frequency so as reduce the frequency and phase differences.

Claims

1. A system for generating an internal clock signal in response to an external clock signal, comprising:

a phase adjustment circuit responsive to said external clock signal and said internal clock signal for producing a phase adjustment signal representing a difference between the phase of said external clock signal and the phase of said internal clock signal;

a frequency adjustment circuit responsive to said external clock signal and said internal clock signal for producing a frequency adjustment signal representing a difference between the frequency of said external clock signal and the frequency of said internal clock signal;

a control value calculator responsive to said phase adjustment signal and said frequency adjustment signal for producing a resulting control signal; and

a signal-controlled oscillator responsive to said resulting control signal for producing said internal clock signal at an internal clock frequency deviating in response to said resulting control signal;

wherein said frequency adjustment circuit comprises a frequency detector responsive to said external clock signal and said internal clock signal for producing an instantaneous value of a frequency error signal indicating a difference between instantaneous frequencies of the internal clock signal and the external clock signal, and

an accumulator coupled to said frequency detector for accumulating instantaneous values of the frequency error signal over a preset time period to produce an accumulated signal indicating an average value of the frequency difference for the preset time period.

2. The system of claim 1, wherein said frequency adjustment circuit further comprises an adjusting circuit coupled to said accumulator for adjusting said accumulated signal to produce said frequency adjustment signal.

3. A system for generating an internal clock signal in response to an external clock signal, comprising:

a phase adjustment circuit responsive to said external clock signal and said internal clock signal for producing a phase adjustment signal representing a difference between the phase of said external clock signal and the phase of said internal clock signal;

a frequency adjustment circuit responsive to said external clock signal and said internal clock signal for producing a frequency adjustment signal representing a difference between the frequency of said external clock signal and the frequency of said internal clock signal;

a control value calculator responsive to said phase adjustment signal and said frequency adjustment signal for producing a resulting control signal; and

a signal-controlled oscillator responsive to said resulting control signal for producing said internal clock signal at an internal clock frequency deviating in response to said resulting control signal,

wherein said frequency adjustment circuit comprises a first counter responsive to said external clock signal and said internal clock signal for counting the number of cycles of the external clock signal during a half cycle of the internal clock signal in which the internal clock signal is at a first logic level.

4. The system of claim 3, wherein said frequency adjustment circuit further comprises a second counter responsive to said external clock signal and said internal clock signal for counting the number of cycles of the external clock signal during a half cycle of the internal clock signal in which the internal clock signal is at a second logic level.

5. The system of claim 4, wherein said frequency adjustment circuit further comprises a third counter responsive to said external clock signal and said internal clock signal for counting the number of cycles of the internal clock signal during a half cycle of the external clock signal in which the external clock signal is at the first logic level.

6. The system of claim 5, wherein said frequency adjustment circuit further comprises a fourth counter responsive to said external clock signal and said internal clock signal for counting the number of cycles of the internal clock signal during a half cycle of the external clock signal in which the external clock signal is at the second logic level.

7. The system of claim 6, wherein said frequency adjustment circuit further comprises first, second, third and fourth adders respectively coupled to said first, second, third and fourth counters for accumulating n-bit counts produced by said first, second, third and fourth counters to generate m-bit accumulated values.

8. The system of claim 7, wherein said frequency adjustment circuit further comprises first, second, third and fourth decoders respectively coupled to said first, second, third and fourth adders to generate first, second, third and fourth frequency control values supplied to said control value calculator.

9. The system of claim 8, wherein said control value calculator is responsive to said first, second, third and fourth frequency control values, and a base value representing said phase adjustment signal, for adding said first and second frequency control values to said base value, and for subtracting said third and fourth frequency control values from said base value.

10. The system of claim 9, wherein said frequency adjustment circuit further comprises a reference current generator for supplying said first, second, third and fourth decoders with reference current to present said first, second, third and fourth frequency control values as first, second, third and fourth frequency control currents.

11. The system of claim 10, wherein said base value is represented by base current.

12. The system of claim 11, wherein said control value calculator is responsive to said first, second, third and fourth frequency control currents and said base current for producing a resulting control current as said resulting control signal supplied to said signal-controlled oscillator to adjust a frequency and phase of said internal clock signal in accordance with a value of said resulting control current.

13. A system for generating an internal clock signal in response to an external clock signal, comprising:

a phase adjustment circuit responsive to said external clock signal and said internal clock signal for producing a phase adjustment signal representing a difference between the phase of said external clock signal and the phase of said internal clock signal;

a frequency adjustment circuit responsive to said external clock signal and said internal clock signal for producing a frequency adjustment signal representing the difference between a frequency of said external clock signal and the frequency of said internal clock signal;

a control value calculator responsive to said phase adjustment signal and said frequency adjustment signal for producing a resulting control signal; and

a signal-controlled oscillator responsive to said resulting control signal for producing said internal clock signal at an internal clock frequency deviating in response to said resulting control signal,

wherein said frequency adjustment circuit comprises a first frequency divider supplied with said internal clock signal for producing a divided internal clock signal at a frequency equal to the frequency of the internal clock signal divided by a preset number,

a second frequency divider supplied with said external clock signal for producing a divided external clock signal at a frequency equal to the frequency of the external clock signal divided by the preset number, and

a first counter coupled to said first frequency divider and supplied with said external clock signal for counting the number of cycles of the external clock signal in a half cycle of the divided internal clock signal.

14. The system of claim 13, wherein said frequency adjustment circuit further comprises a second counter coupled to said second frequency divider and supplied with said internal clock signal for counting the number of cycles of the internal clock signal in a half cycle of the divided external clock signal.

15. The system of claim 14, wherein said frequency adjustment circuit further comprises first and second adders respectively coupled to said first and second counters for accumulating n-bit counts produced by said first and second counters to generate m-bit accumulated values.

16. The system of claim 15, wherein said frequency adjustment circuit further comprises first and second decoders respectively coupled to said first and second adders to generate first and second frequency control values supplied to said control value calculator.

17. The system of claim 16, wherein said control value calculator is responsive to said first and second frequency control values, and a base value represented by said phase adjustment signal for adding said first frequency control value to said base value, and for subtracting said second frequency control value from said base value.

18. A system for generating an internal clock signal in response to an external clock signal, comprising:

a phase adjustment circuit responsive to said external clock signal and said internal clock signal for producing a phase adjustment signal representing a difference between the phase of said external clock signal and the phase of said internal clock signal;

a frequency adjustment circuit responsive to said external clock signal and said internal clock signal for producing a rough frequency adjustment signal representing a difference between the frequency of said external clock signal and the frequency of said internal clock signal;

a control value calculator responsive to said phase adjustment signal and said rough frequency adjustment signal for producing a resulting control signal;

a signal-controlled oscillator responsive to said resulting control signal for producing said internal clock signal at an internal clock frequency deviating in response to said resulting control signal; and

a fine adjustment circuit supplied with said external clock signal for providing a fine frequency tuning signal to said control value calculator, in addition to the rough frequency adjustment signal provided by said frequency adjustment circuit, and the phase adjustment signal provided by said phase adjustment circuit.

19. The system of claim 18, wherein said fine adjustment circuit comprises a delay monitor for delaying said external clock signal by a delay amount corresponding to a period of said internal clock signal.

20. The system of claim 19, wherein said fine adjustment circuit further comprises a comparator for comparing a delayed external clock signal produced by said delay monitor with said external clock signal to generate a fine control signal as said fine frequency tuning signal.

21. The system of claim 20, wherein said control value calculator is responsive to said fine control signal for modifying said resulting control signal.

22. The system of claim 18, wherein said fine adjustment circuit comprises a delay model responsive to said external clock signal for producing a first output signal delayed by a first delay time smaller than a period of said internal clock signal generated by said signal-controlled oscillator, and for producing a second output signal delayed by a second delay time larger than the period of said internal clock signal generated by said signal-controlled oscillator.

23. The system of claim 22, wherein said fine adjustment circuit further comprises a logic circuit coupled to said delay model and supplied with an input signal corresponding to said external clock signal to said delay model for determining logic levels of said first and second output signals when said input signal goes from a first level to a second level.

24. The system of claim 23, wherein said logic circuit is arranged to produce a down signal when both said first and second output signals are at the first level when said input signal goes from the first level to the second level.

25. The system of claim 24, wherein said logic circuit is arranged to produce an up signal when both said first and second output signals are at the second level when said input signal goes from the first level to the second level.

26. The system of claim 25, wherein said control value calculator is responsive to said logic circuit for increasing a value of said resulting control signal in response to said up signal, and for decreasing the value of said resulting control signal in response to said down signal.

27. The system of claim 26, wherein said fine adjustment circuit further comprises a frequency divider coupled to said delay model for producing a divider external clock signal at a frequency equal to the frequency of said external clock signal divided by a predetermined amount.

28. The system of claim 26, wherein said fine adjustment circuit further comprises a first adder coupled to said logic circuit for accumulating instantaneous values of the up signal to generate m-bit accumulated values of the up signal.

29. The system of claim 28, wherein said fine adjustment circuit further comprises a second adder coupled to said logic circuit for accumulating instantaneous values of the down signal to generate m-bit accumulated values of the down signal.

30. The system of claim 29, wherein said fine adjustment circuit further comprises first and second decoders respectively coupled to said first and second adders to generate first and second fine tuning values supplied to said control value calculator as said fine frequency tuning signal.

31. The system of claim 30, wherein said control value calculator is responsive to said first and second fine tuning values, and a base value representing said phase adjustment signal for adding said first fine tuning value to said base value, and for subtracting said second fine tuning values from said base value to produce said resulting control signal.

32. The system of claim 31, wherein said control value calculator is further responsive to a frequency control value produced by said frequency adjustment circuit as said rough frequency adjustment signal for modifying said resulting control signal in accordance with said frequency control value.

33. The system of claim 32, wherein said signal-controlled oscillator comprises a ring oscillator having k serially connected inverter stages.

34. The system of claim 33, wherein said delay model comprises more than 2k serially connected delay stages similar to the inverter stages of said ring oscillator.

35. The system of claim 34, wherein said delay model is arranged to produce said first output signal at an output of delay stage 2k−

l, where l is an integer.

36. The system of claim 35, wherein said delay model is arranged to produce said second output signal at an output of delay stage 2k+l.

37. The system of claim 36, wherein said fine adjustment circuit further comprises a reference current generator for supplying said first and second decoders with reference current to present said first and second fine values as first and second fine tuning currents.

38. The system of claim 37, wherein said base value is represented by a base current, and said frequency control value is represented by a frequency control current.

39. The system of claim 38, wherein said control value calculator is responsive to said first and second fine tuning currents, said frequency control current and said base current for producing a resulting control current representing the resulting control signal supplied to said ring oscillator to tune the frequency of said ring oscillator in accordance with said resulting control current.

40. A method of producing an internal clock signal in synchronization with an external clock signal, comprising the steps of:

comparing the phase of said internal clock signal with the phase of said external clock signal to produce a phase adjustment signal representing differences in phase and frequency between said internal clock signal and said external clock signal,

comparing the frequency of said internal clock signal with the frequency of said external clock signal independently from said step of phase comparing, to produce a frequency adjustment signal representing the difference between the frequency of said internal clock signal and the frequency of said external clock signal;

producing a control signal representing said phase adjustment signal and said frequency adjustment signal;

controlling a signal-controlled oscillator by said control signal to produce said internal clock signal synchronized with said external clock signal, wherein said steps of phase comparing and frequency comparing are carried out by separate circuits; and

further

fine tuning said signal-controlled oscillator when the frequency of said internal clock signal is close to the frequency of said external clock signal,

wherein said step of fine tuning comprises a step of delaying the external clock signal by a delay time corresponding to a period of said internal clock signal.

41. The method of claim 40, wherein said step of fine tuning further comprises a step of comparing a delayed external clock signal with the external clock signal to produce a fine tuning signal.

42. The method of claim 41, wherein said control signal is produced so as to represent said phase adjustment signal, said frequency adjustment signal and said fine tuning signal.

43. A system for generating an internal clock signal in response to a reference clock signal, comprising:

a phase adjustment circuit responsive to said reference clock signal and said internal clock signal for producing a phase adjustment signal representing a difference between the phase of said reference clock signal and the phase of said internal clock signal;

a frequency adjustment circuit responsive to said reference clock signal and said internal clock signal for producing a frequency adjustment signal representing a difference between the frequency of said reference clock signal and the frequency of said internal clock signal;

a control value calculator responsive to said phase adjustment signal and said frequency adjustment signal for producing a resulting control signal; and

a signal-controlled oscillator responsive to said resulting control signal for producing said internal clock signal at an internal clock frequency deviating in response to said resulting control signal,

said frequency adjustment circuit including counter circuitry responsive to said reference clock signal and said internal clock signal for counting the number of cycles of said reference clock signal and said internal clock signal whichever is greater in frequency in a predetermined number of cycle(s) of said reference clock signal and said internal clock signal whichever is smaller in frequency, even when a relation in magnitude of frequency between the reference clock signal and the internal clock signal is changed.

44. The system of claim 43, wherein said counter circuitry includes a first counter for counting the number of the cycles of said reference clock signal in the predetermined number of the cycle(s) of said internal clock signal, and a second counter for counting the number of the cycles of said internal clock signal in the predetermined number of the cycle(s) of said reference clock signal.

45. A system for generating an internal clock signal in response to a reference clock signal, comprising:

a phase adjustment circuit responsive to said reference clock signal and said internal clock signal for producing a phase adjustment signal representing a difference between the phase of said reference clock signal and the phase of said internal clock signal;

a frequency adjustment circuit responsive to said reference clock signal and said internal clock signal for producing a frequency adjustment signal representing a difference between the frequency of said reference clock signal and the frequency of said internal clock signal;

a control value calculator responsive to said phase adjustment signal and said frequency adjustment signal for producing a resulting control signal; and

a signal-controlled oscillator responsive to said resulting control signal for producing said internal clock signal at an internal clock frequency deviating in response to said resulting control signal,

said frequency adjustment circuit including counter circuitry responsive to said reference clock signal and said internal clock signal for counting the number of cycles of said reference clock signal in a predetermined window period, regardless of which of the reference clock signal and the internal clock signal is greater in frequency, said predetermined window period being N time(s) the cycle period of said internal clock signal even when a relation in frequency magnitude between the reference clock signal and the internal clock signal is changed, with N being an integer.