Digital-analog current converter

• US 6,337,647 B1
• Filed: 09/18/2000
• Issued: 01/08/2002
• Est. Priority Date: 09/17/1999
• Status: Expired due to Fees

• Current Assignee: e2v semiconductors SAS
• Original Assignee: e2v semiconductors SAS
• Inventors: Icord, Isabelle, Masson, Thierry
• Primary Examiner(s): Young, Brian
• Assistant Examiner(s): NGUYEN, JOHN B
• Application Number:
  US09/664,343
• Time in Patent Office: 477 Days
• Field of Search: 341/150, 341/144, 341/166, 341/145, 341/147, 341/134, 341/135, 341/136, 341/152, 341/158, 332/109, 340/347.DA, 326/86
• US Class Current: 341/150
• CPC Class Codes: H03M 1/0863 of switching transients, e.g. glitches
• CPC Class Codes: H03M 1/66 Digital/analogue converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 3/372 Jitter reduction
• CPC Class Codes: H03M 3/374 Relaxation of settling time constraints, e.g. slew rate enhancement

Abstract

A digital-analog current converter receives, at input, a succession of bits of a binary signal and delivers, at output, sampled by a clock signal, a positive or negative current depending on the state of the input bit. The converter comprises at least one circuit to control the build-up time of the output current of the converter, comprising a capacitor and a circuit to charge this capacitor controlled by the clock signal. The build-up time is controlled by the charging of a capacitor at a constant current up to a reference voltage. The circuit to control the build-up time of the output current may comprise at least two reference voltages, the capacitor being charged and then discharged between these two voltages. The build-up time of the output current is then the sum of the time taken to charge the capacitor and the time taken to discharge the capacitor. The charging and discharging current of the capacitor can be sent directly into the output load of the converter by means of selector switches and current mirrors. Two capacitors are used and are they are charged and discharged. While one of the capacitors gets charged, the other gets discharged. The disclosure can be applied especially to sigma-delta type digital-analog converters.

Claims

1. A digital-analog current converter having at least one binary input receiving a succession of bits that each have one or another of two binary states and at least one clock input receiving a clock signal, the digital-analog current converter being configured to provide a positive value or a negative value of output current on a converter output depending on the binary state of each of the succession of bits at the binary input, wherein the digital-analog current converter further comprises at least one time control circuit to control a time duration of the positive value and the negative value of the output current on the digital-analog current converter output, the at least one time control circuit comprising:

at least one timing capacitor; and

at least one timing control circuit, the at least one timing control circuit including,

a first clock input receiving the clock signal, and

a charge output connected to the at least one timing capacitor,

wherein the at least one timing control circuit is configured to supply a first constant current from a first constant current source to the charge output to charge the at least one timing capacitor at a time determined by the clock signal, the charging of the at least one timing capacitor being terminated by the at least one timing control circuit when the charge on the at least one timing capacitor reaches a first reference voltage level.

2. The digital-analog current converter according to claim 1, wherein the at least one timing control circuit further comprises at least:

a switch configured to be controlled by the clock signal in such a way that the switch is on when the clock signal is in a first state and off when the clock signal is in a second state, the switch being connected between a power supply terminal and a terminal of the first constant current source, the other terminal of the first constant current source being connected to a ground potential terminal, with the at least one timing capacitor being wired between the charge output connected to a junction point between the switch and the first constant current source and the ground potential terminal, the first constant current flowing into the switch when the switch is open and into the charge output connected to the at least one timing capacitor when the switch is closed; and

an operational amplifier having a positive input connected to receive the first reference voltage level and a negative input connected to an emitter of a transistor that is also connected to the junction point, the transistor further having a base connected to the output of the operational amplifier and a collector connected to the positive supply terminal,

wherein when the voltage at the terminals of the at least one timing capacitor being charged reaches the first reference voltage level, the output of the operational amplifier controls the base of the transistor to place the transistor in an on state so that the first constant current is shunted by the transistor and the charging of the at least one timing capacitor cannot exceed a value determined by the first reference voltage level.

3. The digital-analog current converter according to claim 1, wherein the at least one timing control circuit is further configured to also control discharge of the at least one timing capacitor at constant current under control of the clock signal and a second reference voltage level, the at least one timing capacitor being discharged to a level determined by the second reference voltage level.

4. The digital-analog current converter according to claim 3, wherein the at least one timing control circuit further comprises:

at least one charge and discharge constant current supply circuit connected to a power supply terminal at a first side of the first constant current source delivering the first constant current that has a second side connected to a first side of a first switch that in turn has a second side connected to a first side of a second switch that in turn has a second side connected to a first side of a second constant current source delivering a second constant current that in turn has a second side connected to a second power supply terminal, the first switch being controlled by a first level of the clock signal and the second switch being controlled by a conjugate second level of the clock signal, the at least one timing capacitor being connected to the charge output and a discharge output of the at least one timing control circuit at a junction point between the first and second switches so that the at least one timing capacitor is charged by the first constant current and discharged by the second constant current from the corresponding one of first and second constant current sources;

at least one first limiting circuit configured to limit voltage at the terminals of the at least one timing capacitor to the first reference voltage level and at least one second limiting circuit configured to limit the voltage at the terminals of the at least one timing capacitor to a second reference voltage level, the at least one first limiting circuit comprising,

a first operational amplifier, and

a first transistor,

wherein the first operational amplifier has a positive input receiving the first reference voltage level and a negative input connected to a collector of the first transistor that is connected to the junction point and an output connected to a base of the first transistor that further has an emitter connected to the second power supply terminal;

the at least one second limiting circuit comprising,

a second operational amplifier, and

a second transistor,

wherein the second operational amplifier has a positive input receiving the second reference voltage level and a negative input connected to an emitter of the second transistor that is connected to the junction point and an output connected to a base of the second transistor that further has a collector connected to the first power supply terminal, and

wherein the first operational amplifier output at the base of the first transistor controls the first transistor to shunt the first constant current from the first constant current source when the voltage at the terminals of the at least one timing capacitor reaches the first reference voltage level and the second operational amplifier output at the base of the second transistor controls the second transistor to shunt the second constant current from the second constant current source when the voltage at the terminals of the at least one timing capacitor reaches the second reference voltage level.

5. The digital-analog current converter according to claim 4, comprising two arms in parallel, each arm comprising:

one of the charge and discharge constant current supply circuits;

a timing capacitor connected between the junction point of the first and second switches of the charge and discharge constant current supply circuit of each arm and an emitter of a third transistor connected to a collector of a fourth transistor;

a third operational amplifier having a positive input connected to a given potential and a negative input connected to a junction point between the third and fourth transistors and the timing capacitor, the output of the third operational amplifier controlling conduction of the third and fourth transistors;

a first current mirror connected with the two arms and a second current mirror connected with the two arms, the first and second current mirrors having a common output providing the output of the digital-analog current converter, with the first current mirror delivering the positive value of the output current and the second current mirror delivering the negative value of the output current;

a first pair of third and fourth switches having a common junction point connected to the third transistor, the third switch being connected by a second terminal to the first current mirror and the fourth switch being connected by a second terminal to a power supply terminal, the third and fourth switches being controlled by each input bit in such a way that the third switch is on when the input bit is in the binary 1 state and the fourth switch is on when the input binary bit is in the binary 0 state, the discharge current of the timing capacitor passing from a first transistor of the first current mirror to the timing capacitor through the third switch and the third transistor when the timing capacitor gets discharged, the discharge current being then present at the output of the first current mirror providing the digital-analog current converter output;

a second pair of fifth and sixth switches having a common junction point connected to the fourth transistor the sixth switch being connected by a second terminal to the second current mirror and the fifth switch being connected by a second terminal to a ground terminal, the fifth and sixth switches being controlled by each input binary bit so that the fifth switch is on when the bit is in the binary 1 state and the sixth switch is on when the input binary bit is in the binary 0 state, the charging current of the timing capacitor passing from a first transistor of the second current mirror to the timing capacitor through the sixth switch and the fourth transistor when the timing capacitor gets charged, the charging current being then present at output of the second current mirror providing the digital-analog current converter output;

wherein the two arms are controlled in phase opposition by the clock signal so that a timing capacitor associated with a first of the two arms is charged while another timing capacitor associated with a second of the two arms is discharged.

6. The digital-analog current converter according to claim 5, wherein the charge and discharge constant current supply circuits for each of the two arms have the same first and second constant current sources.

7. The digital-analog current converter according to any one of claims 1-6, wherein the output current from the digital-analog current converter is applied to a filter.

8. The digital-analog current converter according to any of claims 1-6, wherein the input succession of bits is given by a sigma-delta converter.