Semiconductor memory device and method for reading data
First Claim
1. A semiconductor memory device comprising:
- a memory cell array with a plurality of arranged memory cells which are selected by a column address and a row address;
a bit line selection circuit for selecting based on said column address a group comprising a predetermined number of bit lines, from bit lines connected with said plurality of memory cells selected by said row address;
a sense amplifier section comprised of sense amplifiers for determining data for each bit line output signals from memory cells input through said plurality of bit lines of said selected group, and outputting data from each of said bit lines as an determination result, a first latch group and a second latch group connected in common to said sense amplifier section, for storing said data of each bit line output from said sense amplifier section, and a latch selection circuit for selecting which of said first latch group data and said second latch group data to output, and then outputting a selection result as read data, wherein during burst read operation, in cases where data of said first latch group is being output as read data, said second latch group stores data from said sense amplifier, and in cases where data of said second latch group is being output as read data, said first latch group stores data from said sense amplifier.
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Accused Products
Abstract
The provision of a semiconductor memory device for which access times in burst mode can be improved with no increase in the chip surface area and with no increase in power consumption. A latch pulse selection circuit 6 uses a control signal CA0T to output an input control signal SALF and a control signal SALS, to a first latch group within a latch circuit 7 as a latch pulse SAL0A, and to a second latch group within the latch circuit 7 as a latch pulse SAL1A, respectively. Based on a control signal YS0˜YS31 input from a column decoder circuit 11, a Y selector 12 is connected to a sense amplifier circuit 8 via Y switches connected to the corresponding digit lines. The sense amplifier circuit 8 comprises 256 sense amplifiers, and performs data evaluations of the signal YD0˜signal YD127 from the Y selector. A latch circuit 7 latches a data signal DT0˜data signal DT127 from the sense amplifier circuit 8 into a first latch group and a second latch group via latch signals SAL0 and SAL1 respectively.
37 Citations
11 Claims
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1. A semiconductor memory device comprising:
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a memory cell array with a plurality of arranged memory cells which are selected by a column address and a row address;
a bit line selection circuit for selecting based on said column address a group comprising a predetermined number of bit lines, from bit lines connected with said plurality of memory cells selected by said row address;
a sense amplifier section comprised of sense amplifiers for determining data for each bit line output signals from memory cells input through said plurality of bit lines of said selected group, and outputting data from each of said bit lines as an determination result, a first latch group and a second latch group connected in common to said sense amplifier section, for storing said data of each bit line output from said sense amplifier section, and a latch selection circuit for selecting which of said first latch group data and said second latch group data to output, and then outputting a selection result as read data, wherein during burst read operation, in cases where data of said first latch group is being output as read data, said second latch group stores data from said sense amplifier, and in cases where data of said second latch group is being output as read data, said first latch group stores data from said sense amplifier. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of reading data from a semiconductor memory device comprising:
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a first step for selecting, from a memory array with a plurality of arranged memory cells which are selected by a column address and a row address, a plurality of said memory cells based on said row address, a second step in which a bit line selection circuit selects a group comprising a predetermined number of bit lines, based on said column address, from bit lines connected with selected said plurality of memory cells, a third step in which a sense amplifier section determines output signals from memory cells, input via said plurality of bit lines of said selected group, using a sense amplifier corresponding with each bit line, and outputs data from each of said bit lines as an evaluation result, a fourth step in which either one of a first latch and a second latch connected in common to said sense amplifier section stores said data of each bit line output from said sense amplifier section, and a fifth step in which a latch selection circuit selects which of said first latch data and said second latch data to output, and then outputs selected latch data as read data, wherein during burst read operation, in cases where data of said first latch is being output as read data, said second latch stores data from said sense amplifier, and in cases where data of said second latch is being output as read data, said first latch stores data from said sense amplifier. - View Dependent Claims (9, 10, 11)
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Specification