Semiconductor memory device

• US 6,337,825 B2
• Filed: 03/22/2001
• Issued: 01/08/2002
• Est. Priority Date: 06/10/1999
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation), Toshiba Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tanzawa, Toru, Atsumi, Shigeru
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): NGUYEN, HIEN N
• Application Number:
  US09/813,811
• Publication Number:
  US 20010009527A1
• Time in Patent Office: 292 Days
• Field of Search: 365/207, 365/205, 365/210, 365/185.2, 365/185.21, 365/185.23, 365/189.09
• US Class Current: 365/207
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells

Abstract

In a semiconductor memory device enabling to lower the source voltage, bit lines (BL) of a memory cell array (11) are selected by a column gate (12) and connected to sense amplifiers (13). Each sense amplifier (13) includes an operational amplifier (OP) having a sense node (SA) as one of its input terminals and a reference node (RE)to be shared with other sense amplifiers (13) as its other input terminal, an NMOS transistor (QN01) as a current source load interposed between the sense node (SA) and a power source (VCC) for each operational amplifier (OP), an NMOS transistor (QN02) as a current source load interposed between the reference node (REF) and the power source (VCC) for each operational amplifier (OP), and a reference voltage generating circuit (21) connected to the reference node (REF) and shared with other sense amplifiers (13) to generate a reference voltage of an intermediate level between voltages of two-valued data output to the sense node SA.

Claims

1. A semiconductor memory device comprising:

a memory cell array in which a plurality of bit lines and a plurality of word lines are arranged to cross each other and current read-out type memory cells are arranged at crossing points thereof;

a decoding circuit for selecting a predetermined number of bit lines and a word line of said memory cell array;

a plurality of sense amplifiers for detecting and amplifying data read out on the predetermined number of bit lines selected from the plurality of bit lines, said sense amplifiers being provided for every I/O line of said memory cell array, said each sense amplifier having a sense node as one input terminal and a reference node as the other input terminal; and

a reference voltage generating circuit for providing a reference voltage having a level between voltages of two-valued data output to said sense node,

wherein said sense node of each sense amplifier is connected to a corresponding I/O line and at least two reference nodes of sense amplifiers is commonly connected to said reference voltage generating circuit.

2. The semiconductor memory device according to claim 1, wherein said sense amplifier includes at least one stage of an operational amplifier.

3. The semiconductor memory device according to claim 1, further comprising a current source load connected to said sense node and a power source terminal.

4. The semiconductor memory device according to claim 3, wherein said current source load is an NMOS transistor having a source connected to said sense node, a drain connected to said power source terminal, and a gate to which a bias voltage lower than the power source voltage is applied.

5. The semiconductor memory device according to claim 3, wherein said current source load is a PMOS transistor having a gate and a drain connected to said sense node, and having a source connected said power source terminal.

6. The semiconductor memory device according to claim 3, wherein said reference voltage generating circuit includes at least one reference cell wherein a current less than a bit line current flowing through said current source load flows therein when a selected memory cell exhibits one of two-valued data.

7. The semiconductor memory device according to claim 2, wherein said operational amplifier includes a pair of differential NMOS transistors whose respective gates are signal input terminals, a current source NMOS transistor connected to a common source of said pair of differential NMOS transistors and having a gate applied with a bias voltage, and loads interposed between drains of said pair of differential NMOS transistors and a power source.

8. The semiconductor memory device according to claim 3, wherein power source switches are provided between said current source loads and a power source terminal.

9. The semiconductor memory device according to claim 1, wherein said reference voltage generator circuit is comprised of m-reference cells each having the same structure as that of the memory cell, the number m being equal to or less than a number n which indicates the number of memory cells simultaneously read out by said plurality of sense amplifiers.

10. The semiconductor memory device according to claim 9, wherein the number m is approximately n/2.

11. A semiconductor memory device comprising:

a memory cell array in which a plurality of bit lines and a plurality of word lines are arranged to cross each other and current read-out type memory cells are arranged at crossing points thereof;

a decoding circuit for selecting a predetermined number of bit lines and a word line of said memory cell array;

a plurality of sense amplifiers for detecting and amplifying data read out on the predetermined number of bit lines selected from the plurality of bit lines, said sense amplifiers being provided for every I/O line of said memory cell array, each sense amplifier having a sense node as one input terminal, which is connected to a corresponding I/O line, and a reference node as the other input terminal; and

a reference voltage generating circuit for providing a reference voltage having a level between voltages of two-valued data output to said sense node, which is connected to said reference node, said reference voltage generating circuit being comprised of m-reference cells each having the same structure as that of said memory cell, the number m being equal to or less than a number n of memory cells simultaneously read out by said plurality of sense amplifiers,

wherein said reference cells are connected to a common word line.

12. The semiconductor memory device according to claim 11, wherein said sense amplifier includes at least one stage of an operational amplifier.

13. The semiconductor memory device according to claim 11, further comprising a current source load connected to said sense node and a power source terminal.

14. The semiconductor memory device according to claim 13, wherein said current source load is an NMOS transistor having a source connected to said sense node, a drain connected to said power source terminal, and a gate to which a bias voltage lower than the power source voltage is applied.

15. The semiconductor memory device according to claim 13, wherein said current source load is a PMOS transistor having a gate and a drain connected to said sense node, and having a source connected said power source terminal.

16. The semiconductor memory device according to claim 13, wherein said reference cells are configured to flow a current less than a current which flows in a bit line through the current source load when the selected memory cell exhibits one state of binary data.

17. The semiconductor memory device according to claim 12, wherein said operational amplifier includes a pair of differential NMOS transistors whose respective gates are signal input terminals, a current source NMOS transistor connected to a common source of said pair of differential NMOS transistors and having a gate applied with a bias voltage, and loads interposed between drains of said pair of differential NMOS transistors and a power source.

18. The semiconductor memory device according to claim 13, wherein power source switches are provided between said current source loads and a power source terminal.

19. The semiconductor memory device according to claim 11, wherein the number m is approximately n/2.

20. A semiconductor memory device comprising:

a memory cell array in which a plurality of bit lines and a plurality of word lines are arranged to cross each other and current read-out type memory cells are arranged at crossing points thereof;

a decoding circuit for selecting a predetermined number of bit lines and a word line of said memory cell array;

a plurality of sense amplifiers for detecting and amplifying data read out on the predetermined number of bit lines selected from the plurality of bit lines, said sense amplifiers being provided for every I/O line of said memory cell array, each sense amplifier having a sense node as one input terminal and a reference node as the other input terminal; and

a reference voltage generating circuit for providing a reference voltage having a level between voltages of two-valued data output to said sense node, which is connected to said reference node, said reference voltage generating circuit being comprised of m-reference cells each having the same structure as that of said memory cell, the number m being equal to or less than a number n of memory cells simultaneously read out by said plurality of sense amplifiers,

wherein a read out voltage of a word line connected to memory cells which is arranged in said memory cell array is equal to that of a reference word line connected to said reference cells.

21. The semiconductor memory device according to claim 20, wherein said sense amplifier includes at least one stage of an operational amplifier.

22. The semiconductor memory device according to claim 20, further comprising a current source load connected to said sense node and a power source terminal.

23. The semiconductor memory device according to claim 22, wherein said current source load is an NMOS transistor having a source connected to said sense node, a drain connected to said power source terminal, and a gate to which a bias voltage lower than the power source voltage is applied.

24. The semiconductor memory device according to claim 22, wherein said current source load is a PMOS transistor having a gate and a drain connected to said sense node, and having a source connected said power source terminal.

25. The semiconductor memory device according to claim 22, wherein said reference cells are configured to flow a current less than a current which flows in a bit line through the current source load when the selected memory cell exhibits one state of binary data.

26. The semiconductor memory device according to claim 21, wherein said operational amplifier includes a pair of differential NMOS transistors whose respective gates are signal input terminals, a current source NMOS transistor connected to a common source of said pair of differential NMOS transistors and having a gate applied with a bias voltage, and loads interposed between drains of said pair of differential NMOS transistors and a power source.

27. The semiconductor memory device according to claim 22, wherein power source switches are provided between said current source loads and a power source terminal.

28. The semiconductor memory device according to claim 20, wherein the number m is approximately n/2.