Data transmission method and game system constructed by using the method

• US 6,338,105 B1
• Filed: 08/17/1998
• Issued: 01/08/2002
• Est. Priority Date: 05/16/1997
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Sega Enterprises
• Original Assignee: Sega Enterprises LTD. (SEGA Sammy Holdings Inc.)
• Inventors: Niizuma, Naoki, Himoto, Atunori
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): PEYTON, TAMMARA R
• Application Number:
  US09/125,382
• Time in Patent Office: 1,240 Days
• Field of Search: 710/72, 710/16, 710/65, 332/101, 332/100
• US Class Current: 710/72
• CPC Class Codes: A63F 13/213 comprising photodetecting means, e.g. cameras, photodiodes or infrared cells A63F13/219, A63F13/655 take precedence
• CPC Class Codes: A63F 13/215 comprising means for detecting acoustic signals, e.g. using a microphone
• CPC Class Codes: A63F 13/23 for interfacing with the game device, e.g. specific interfaces between game controller and console
• CPC Class Codes: A63F 13/235 using a wireless connection, e.g. infrared or piconet
• CPC Class Codes: A63F 13/28 responding to control signals received from the game device for affecting ambient conditions, e.g. for vibrating players' seats, activating scent dispensers or affecting temperature or light controlling the output signals based on the game progress A63F13/50
• CPC Class Codes: A63F 13/54 involving acoustic signals, e.g. for simulating revolutions per minute [RPM] dependent engine sounds in a driving game or reverberation against a virtual wall
• CPC Class Codes: A63F 13/95 Storage media specially adapted for storing game information, e.g. video game cartridges
• CPC Class Codes: A63F 2300/1025 details of the interface with the game device, e.g. USB version detection
• CPC Class Codes: A63F 2300/1031 using a wireless connection, e.g. Bluetooth, infrared connections
• CPC Class Codes: A63F 2300/1081 Input via voice recognition
• CPC Class Codes: A63F 2300/1087 comprising photodetecting means, e.g. a camera
• CPC Class Codes: A63F 2300/206 Game information storage, e.g. cartridges, CD ROM's, DVD's, smart cards
• CPC Class Codes: A63F 2300/302 specially adapted for receiving control signals not targeted to a display device or game input means, e.g. vibrating driver's seat, scent dispenser
• CPC Class Codes: A63F 2300/6081 generating an output signal, e.g. under timing constraints, for spatialization
• CPC Class Codes: A63F 2300/8088 involving concurrently several players in a non-networked game, e.g. on the same game console
• CPC Class Codes: H01R 2107/00 Four or more poles
• CPC Class Codes: H01R 2201/06 for computer periphery
• CPC Class Codes: H01R 24/60 Contacts spaced along planar side wall transverse to longitudinal axis of engagement
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines

Abstract

To provide a new data transmission system between a game device and related peripheral devices, and a device using same.

Serial transmission data is divided into an odd-numbered bit sequence and an even-numbered bit sequence. Each bit of the odd-numbered bit sequence data is distributed respectively between pulses of a first pulse sequence signal having a constant interval, thereby forming a first pulse sequence signal (SDCKA). Each bit of the even-numbered bit sequence data is distributed respectively between pulses of a second pulse sequence signal having a constant interval, thereby forming a second pulse sequence signal (SDCKB). The respective time axes are adjusted such that the clock component of the first pulse sequence signal is located in the data section of the second pulse sequence signal, and the clock component of the second pulse sequence signal is located in the data section of the first pulse sequence signal. Data is transmitted using these adjusted first and second pulse sequence signals (SDCKA, SDCKB).

Claims

1. A data transmission system comprising:

a data transmitting device which is arranged to transmit data serially via a first data signal and a second data signal, said first data signal containing a first clock signal including a sequence of first pulses and odd-numbered bits of said data, the odd-numbered bits of data being arranged in the first data signal in order between the sequence of first pulses of said first clock signal;

said second data signal containing a second clock signal including a sequence of second pulses having the same frequency as said sequence of first pulses of said first clock signal and including even-numbered bits of said data, the even-numbered bits of data being arranged in order between the sequence of second pulses of said second clock signal;

the data bits in said first and second data signals being allocated such that a data bit in one of the first and second data signals is located at a timing corresponding to a clock signal component of the clock signal in the other of the first and second data signals.

2. The data transmission system according to claim 1, further comprising a data receiving device which is arranged to receive the first and second data signals and retrieve the data out of the received first and second data signals by alternately latching a potential level of one of said first and second data signals at the timing of the clock signal component of the other of said first and second data signals.

5. The data transmission system according to claim 1, wherein said clock signal component is detected based on an edge of one of the pulses in said first and second clock signals.

3. A data transmission system comprising:

a data transmitter which is arranged to transmit serially data bits of data by allocating the data bits of the data into a first data signal and a second data signal;

said first and second data signals being arranged to have a format including a data frame defined according to a transmission format and including a start pattern, a data pattern and an end pattern;

said start pattern having a data format wherein, while said first data signal is maintained at a predetermined value of a constant potential level, said second data signal including a first sequence of pulses is transmitted;

said data pattern having a data format that includes a sequence of clock pulses in each of said first and second data signals so that said data bits of the data alternately a successively allocated among said clock pulses being shifted relative to one another by a prescribed amount along a time axis; and

said end pattern having a data format wherein, while said second data signal is maintained at a predetermined value of a constant potential level, said first data signal including a second sequence of pulses is transmitted.

4. An information storage medium for use with a computer system which is installed in said data transmission system according to claim 3 for collecting control signals from a peripheral device, said information storage medium storing computer game software programs for causing said computer system to operate as a game device in response to control signals from a peripheral device.

6. A data transmission system comprising:

a data transmitter arranged to serially transmit data composed of plural data bits by allocating the data bits of the data into a first data signal and a second data signal;

said first data signal containing a first clock signal having a sequence of pulses and a first set of data bits including every other data bit of said data and arranged such that said every other data bit of said data included in said first set of data bits is allocated in order between said pulses of said first clock signal;

said second data signal containing a second clock signal having a sequence of pulses and a second set of data bits including every other data bit of said data not included in said first set of data bits and arranged such that said every other data bit of said data included in said second set of data bits is allocated in order between said pulses of said second clock signal; and

the data bits in said first and second data signals being allocated such that a data bit in one of said first and second data signals is located at a timing corresponding to a clock signal component of the clock signal in the other of said first and second data signals.

7. The data transmission system according to claim 6, further comprising a data receiver arranged to receive said first and second data signals and adapted to retrieve the data out of the received first and second data signals by alternately latching a potential level of one of said first and second data signals at the timing of the clock signal component of the other of said first and second data signals.

8. The data transmission system according to claim 6, wherein said clock signal component is detected based upon one of a rising edge and a falling edge of each pulse in said first and second clock signals.

9. A data transmission system:

a game device having a plurality of peripheral ports each arranged to send data to, and collect data from, a peripheral device, said game device executing a software program in response to data received from one of said plurality of peripheral ports;

at least one peripheral device connectable to one of said peripheral ports via a transmission path and arranged to receive data from, and send data to, said game device;

said game device and said peripheral device each including data control means for interactively transmitting data via said transmission path by converting data bits of the data to be sent into a pair of data signals each including a data frame;

one data frame of said pair of data signals including a start pattern carrying data start information, a data pattern and an end pattern carrying data end information;

said data pattern having a data format including a sequence of clock pulses in each of said pair of data signals and bits of the data being alternately allocated in order between said clock pulses in said pair of data signals, a timing of clock pulses being shifted between said sequences of clock pulses of said pair of data signals relative to each other by a period such that a data bit in one of said pair of data signals is located at a timing corresponding to a clock signal component of a clock pulse in the other of said pair of data signals;

said game device and said peripheral device each including data retrieving means for retrieving the data out of the received pair of data signals by alternately latching a potential level of one of said pair of data signals at the timing of the clock signal component of the other of said pair of data signals.

10. The data transmission system according to claim 9, wherein said start pattern has a data format such that a first of said pair of data signals transmits a first train of pulses while a second of said pair of data signals maintains a constant potential level;

and

said end pattern has a data format such that a first of said pair of data signals transmits a second train of pulses while a second of said pair of data signals maintains a constant potential level.

11. A data communication system comprising:

a data generator for converting data into serial data on a time axis in a form of first and second serial data signals, the data generator converting data bits of said data by inserting the data bits between each pulse of a transmission clock pulse sequence and shifting the first and second serial data signals relative to each other by an appropriate amount on the time axis so that each pulse edge of one of the first and second serial data signals is located in a data section of the other of the first and second serial data signals.

12. The data communication system according to claim 11, further comprising a serial bus operatively connected to the data generator and receiving the first and second serial data signals from the data generator;

and

a data receiver operatively connected to the serial bus and arranged to receive the first and second serial data signals from the data generator via the serial bus.

13. The data communication system according to claim 12, wherein the data receiver receives the first and second serial data signals and retrieves data out of the first and second serial data signals by alternately latching a potential level of one of the first and second serial data signals at a timing of a clock signal component of the other of the first and second serial data signals.

14. The data communication system according to claim 11, wherein said data generator includes a circuit for converting data to the first and second serial data signals, the circuit including at least one shift register, a shift clock and at least one selector.

15. The data communication system according to claim 14, wherein a plurality of even numbered bits of the data are supplied to input terminals of the at least one shift register and data is shifted by the shift clock and the shifted data is supplied from an output terminal of the at least one selector as serial data.

16. The data communication system according to claim 15, wherein a clock signal is input to the at least one selector and the at least one selector selects serial data from an output terminal of the at least one selector in accordance with a High level of the shift clock signal and selects a clock signal in accordance with a Low level of the shift clock signal.

17. The data communication system according to claim 14, wherein a plurality of odd numbered bits of the data are supplied to input terminals of the at least one shift register and data is shifted by the shift clock and the shifted data is supplied from an output terminal of the at least one selector as serial data.

18. The data communication system according to claim 17, wherein a clock signal is input to the at least one selector and the at least one selector selects serial data from an output terminal of the at least one selector in accordance with a High level of the shift clock signal and selects a clock signal in accordance with a Low level of the shift clock signal.

19. The data communication system according to claim 11, wherein serial clock data in the first and second serial data signals alternately form negative edges.

20. The data communication system according to claim 11, wherein the data receiver receives the first and second serial data signals and the data receiver latches a data section of one of the first and second serial data signals in accordance with a negative edge timing of a waveform of the other of the first and second serial data signals so that the data section is read out to produce reproduction data.

21. The data communication system according to claim 11, wherein the data receiver receives the first and second serial data signals and the data receiver latches a data section of one of the first and second serial data signals in accordance with a positive edge timing of a waveform of the other of the first and second serial data signals so that the data section is read out to produce reproduction data.

22. The data communication system according to claim 11, wherein the first and second serial data signals are generated such that falling edges of each of the first and second serial data signals always occur alternately when data is being transmitted in the other of the first and second serial data signals.

23. The data communication system according to claim 11, wherein said first and second serial data signals have a format including a data frame defined according to a transmission format and including a start pattern, a data pattern and an end pattern;

said start pattern having a data format wherein, while said first serial data signal is maintained at a constant potential level, said second serial data signal including a first sequence of pulses is transmitted;

said data pattern having a data format that includes a sequence of clock pulses in each of said first and second serial data signals including bits of data alternately and successively allocated among said clock pulses of said first and second serial data signals, said sequences of clock pulses being shifted relative to one another by a prescribed amount along a time axis; and

said end pattern having a data format wherein, while said second serial data signal is maintained at a constant potential level, said first serial data signal including a second sequence of pulses is transmitted.

24. The data communication system according to claim 23, wherein the data communication system is provided in a game device having a plurality of peripheral ports, said data pattern comprises a command and a parameter, said parameter comprises an address of one of a plurality of peripheral devices connected to the game device via the plurality of peripheral ports, an address of the peripheral port with which said one of said plurality of peripheral devices is connected and data to be transmitted from the game device to said one of said plurality of peripheral devices.

25. The data communication system according to claim 11, wherein said first serial data signal includes odd-numbered bits of said data and said second serial data signal includes even-numbered bits of said data to be transmitted to said at least one peripheral device.