Coprocessor-integrated packet-type memory LSI, packet-type memory/coprocessor bus, and control method thereof

• US 6,338,108 B1
• Filed: 04/14/1998
• Issued: 01/08/2002
• Est. Priority Date: 04/15/1997
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Motomura, Masato
• Primary Examiner(s): Beausoleil, Robert
• Assistant Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US09/059,377
• Time in Patent Office: 1,365 Days
• Field of Search: 710/110, 710/113, 710/119, 710/126, 710/129, 365/233, 365/230.02, 365/230.03, 365/221, 712/6, 712/10, 712/11, 712/17, 711/105-106, 711/5, 711/104, 711/111, 711/147
• US Class Current: 710/110
• CPC Class Codes: G06F 13/4243 with synchronous protocol

Abstract

A memory section and coprocessor sections in a coprocessor-integrated packet-type DRAM are provided with unique memory device ID and coprocessor device IDs respectively. The coprocessor-integrated packet-type DRAMs are connected to a single bus master type packet-type memory/coprocessor bus via external I/O terminals. A request packet is transmitted by the bus master to the packet-type memory/coprocessor bus, and each of the coprocessor-integrated packet-type DRAMs which received the request packet verifies a device ID field in the request packet against the memory device ID and the coprocessor device IDs stored in the coprocessor-integrated packet-type DRAM. If the device ID field matched, the request packet is decoded and memory access to the memory section or coprocessor access to the coprocessor section requested by the request packet is executed. By the access to the coprocessor sections, control of arithmetic logic operation functions of the coprocessor sections including ‘operation parameter writing’, ‘operation start request’, ‘operation status reading’, ‘operation result request’, etc. can be executed by the bus master. High speed calculation is executed by the on-chip coprocessor sections taking advantage of wide data bandwidth internal data transmission against the memory section.

Claims

1. A coprocessor-integrated packet-type memory LSI to be connected to a packet-type memory/coprocessor bus out of the coprocessor-integrated packet-type memory LSI via an external I/O terminal having a desired number of signal terminals, comprising a memory section, a control section, an interface section, and a desired number of coprocessor sections, wherein:

a memory device ID and coprocessor device IDs are assigned to the memory section and the coprocessor sections respectively and are stored in the coprocessor-integrated packet-type memory LSI, in which the memory device ID and the coprocessor device IDs are assigned so that each of them can uniquely designate one memory section or one coprocessor section out of all of the memory sections and the coprocessor sections in all of the coprocessor-integrated packet-type memory LSIs which are connected to the packet-type memory/coprocessor bus.

2. A coprocessor-integrated packet-type memory LSI as claimed in claim 1, wherein:

the memory section includes a memory core section and a memory control register section including a desired number of memory control registers,

the coprocessor section includes an operation core section, an operation control section, and an operation control register section including a desired number of operation control registers,

the control section and the memory section are connected by an internal memory data bus, and

the control section and the coprocessor sections are connected by internal coprocessor data buses.

3. A coprocessor-integrated packet-type memory LSI as claimed in claim 2, wherein the memory core section is composed of dynamic random access memory.

4. A packet-type memory/coprocessor bus for connecting a bus master and a desired number of coprocessor-integrated packet-type memory LSIs of claim 1, 2 or 3 wherein:

the packet-type memory/coprocessor bus is a single bus master type bus needing no arbitration for its bus exclusive ownership to be executed by the bus master when the bus master transmits a packet to the packet-type memory/coprocessor bus, in which two types of packets including a request packet and a write data packet can be transmitted by the bus master to the packet-type memory/coprocessor bus, and a read data packet can be transmitted by the coprocessor-integrated packet-type memory LSI to the packet-type memory/coprocessor bus.

5. A packet-type memory/coprocessor bus for connecting a bus master and a desired number of coprocessor-integrated packet-type memory LSIs of claim 1, 2 or 3, wherein:

the packet-type memory/coprocessor bus is a single bus master type bus needing no arbitration for its bus exclusive ownership to be executed by the bus master when the bus master transmits a packet to the packet-type memory/coprocessor bus, in which two types of packets including a request packet and a write data packet can be transmitted by the bus master to the packet-type memory/coprocessor bus, and two types of packets including a read data packet and an acknowledge packet can be transmitted by the coprocessor-integrated packet-type memory LSI to the packet-type memory/coprocessor bus.

6. A packet-type memory/coprocessor bus as claimed in claim 4, wherein the request packet includes:

a device ID field for designating the destination of the request packet out of all of the memory sections and the coprocessor sections in all of the coprocessor-integrated packet-type memory LSIs which are connected to the packet-type memory/coprocessor bus;

a command field for designating a process which the request packet requests; and

a parameter filed for designating parameters which are necessary for the execution of the process which is requested by the request packet.

7. A packet-type memory/coprocessor bus as claimed in claim 5, wherein the request packet includes:

a device ID field for designating the destination of the request packet out of all of the memory sections and the coprocessor sections in all of the coprocessor-integrated packet-type memory LSIs which are connected to the packet-type memory/coprocessor bus;

a command field for designating a process which the request packet requests; and

a parameter filed for designating parameters which are necessary for the execution of the process which is requested by the request packet.

8. A packet-type memory/coprocessor bus as claimed in claim 6, wherein the device ID field has a fixed field length regardless of whether the device ID field designates a memory section or a coprocessor section, and the command field also has a fixed field length regardless of whether the device ID field designates a memory section or a coprocessor section.

9. A packet-type memory/coprocessor bus as claimed in claim 7, wherein the device ID field has a fixed field length regardless of whether the device ID field designates a memory section or a coprocessor section, and the command field also has a fixed field length regardless of whether the device ID field designates a memory section or a coprocessor section.

10. A packet-type memory/coprocessor bus as claimed in claim 6, wherein the device ID field has a fixed field length regardless of whether the device ID field designates a memory section or a coprocessor section, and the field length of the command field varies depending on whether the device ID field designates a memory section or a coprocessor section.

11. A packet-type memory/coprocessor bus as claimed in claim 7, wherein the device ID field has a fixed field length regardless of whether the device ID field designates a memory section or a coprocessor section, and the field length of the command field varies depending on whether the device ID field designates a memory section or a coprocessor section.

12. A packet-type memory/coprocessor bus as claimed in claim 8 including:

a control bus which is a unidirectional bus from the bus master to the coprocessor-integrated packet-type memory LSI; and

a data bus which is a bidirectional bus between the bus master and the coprocessor-integrated packet-type memory LSI.

13. A packet-type memory/coprocessor bus as claimed in claim 9 including:

a control bus which is a unidirectional bus from the bus master to the coprocessor-integrated packet-type memory LSI; and

a data bus which is a bidirectional bus between the bus master and the coprocessor-integrated packet-type memory LSI.

14. A packet-type memory/coprocessor bus as claimed in claim 10 including:

a control bus which is a unidirectional bus from the bus master to the coprocessor-integrated packet-type memory LSI; and

a data bus which is a bidirectional bus between the bus master and the coprocessor-integrated packet-type memory LSI.

15. A packet-type memory/coprocessor bus as claimed in claim 11 including:

a control bus which is a unidirectional bus from the bus master to the coprocessor-integrated packet-type memory LSI; and

a data bus which is a bidirectional bus between the bus master and the coprocessor-integrated packet-type memory LSI.

16. A packet-type memory/coprocessor bus as claimed in claim 8 including:

a request bus which is a unidirectional bus from the bus master to the coprocessor-integrated packet-type memory LSI; and

a response bus which is a unidirectional bus from the coprocessor-integrated packet-type memory LSI to the bus master.

17. A packet-type memory/coprocessor bus as claimed in claim 9 including:

a request bus which is a unidirectional bus from the bus master to the coprocessor-integrated packet-type memory LSI; and

a response bus which is a unidirectional bus from the coprocessor-integrated packet-type memory LSI to the bus master.

18. A packet-type memory/coprocessor bus as claimed in claim 10 including:

a request bus which is a unidirectional bus from the bus master to the coprocessor-integrated packet-type memory LSI; and

a response bus which is a unidirectional bus from the coprocessor-integrated packet-type memory LSI to the bus master.

19. A packet-type memory/coprocessor bus as claimed in claim 11 including:

a request bus which is a unidirectional bus from the bus master to the coprocessor-integrated packet-type memory LSI; and

a response bus which is a unidirectional bus from the coprocessor-integrated packet-type memory LSI to the bus master.

20. A method for controlling the coprocessor-integrated packet-type memory LSI of claim 1, 2 or 3, comprising the steps of:

a reception step in which the interface section receives the request packet from the packet-type memory/coprocessor bus of claim 6 or 7 via the external I/O terminal;

a verification step in which the control section verifies the device ID field in the request packet against the memory device ID and the coprocessor device IDs stored in the coprocessor-integrated packet-type memory LSI;

a decoding step in which the control section decodes the command field in the request packet, only in the case where the device ID field designates any of the memory device ID and the coprocessor device IDs stored in the coprocessor-integrated packet-type memory LSI; and

an instruction step in which the control section instructs the memory section or the coprocessor section designated by the device ID field to execute the process which is requested by the request packet.

21. A coprocessor-integrated packet-type memory LSI as claimed in claim 1, wherein the coprocessor-integrated packet-type memory LSI is controlled by the method of claim 20, and the coprocessor-integrated packet-type memory LSI further comprises:

a memory device ID register for storing the memory device ID of the memory section;

one or more coprocessor device ID registers for storing the coprocessor device IDs of the coprocessor sections respectively; and

a memory/coprocessor device ID verification circuit connected with the memory device ID register and the coprocessor device ID registers, for parallelly executing the verification of the device ID field in the request packet against the memory device ID stored in the memory device ID register and the verification of the device ID field in the request packet against the coprocessor device IDs stored in the coprocessor device ID registers respectively, and thereby judging whether or not the device ID field designates each of the memory section and the coprocessor sections in the coprocessor-integrated packet-type memory LSI.

22. A coprocessor-integrated packet-type memory LSI as claimed in claim 2, wherein the coprocessor-integrated packet-type memory LSI is controlled by the method of claim 20, and the coprocessor-integrated packet-type memory LSI further comprises:

a memory device ID register for storing the memory device ID of the memory section;

one or more coprocessor device ID registers for storing the coprocessor device IDs of the coprocessor sections respectively; and

a memory/coprocessor device ID verification circuit connected with the memory device ID register and the coprocessor device ID registers, for parallelly executing the verification of the device ID field in the request packet against the memory device ID stored in the memory device ID register and the verification of the device ID field in the request packet against the coprocessor device IDs stored in the coprocessor device ID registers respectively, and thereby judging whether or not the device ID field designates each of the memory section and the coprocessor sections in the coprocessor-integrated packet-type memory LSI.

23. A coprocessor-integrated packet-type memory LSI as claimed in claim 3, wherein the coprocessor-integrated packet-type memory LSI is controlled by the method of claim 20, and the coprocessor-integrated packet-type memory LSI further comprises:

a memory device ID register for storing the memory device ID of the memory section;

one or more coprocessor device ID registers for storing the coprocessor device IDs of the coprocessor sections respectively; and

a memory/coprocessor device ID verification circuit connected with the memory device ID register and the coprocessor device ID registers, for parallelly executing the verification of the device ID field in the request packet against the memory device ID stored in the memory device ID register and the verification of the device ID field in the request packet against the coprocessor device IDs stored in the coprocessor device ID registers respectively, and thereby judging whether or not the device ID field designates each of the memory section and the coprocessor sections in the coprocessor-integrated packet-type memory LSI.

24. A coprocessor-integrated packet-type memory LSI as claimed in claim 22, wherein the memory device ID register is provided as one of the memory control registers in the memory control register section of the memory section, and the coprocessor device ID register is provided as one of the operation control registers in the operation control register section of the coprocessor section.

25. A method as claimed in claim 20, wherein in the decoding step, the control section employs different decoding methods for decoding the command field depending on whether the device ID field of the request packet designates a memory section or a coprocessor section, in which a command field with a particular bit pattern can designate different process requests depending on whether the device ID field designates a memory section or a coprocessor section.

26. A method as claimed in claim 20, wherein in the case where the device ID field in the request packet designated the memory section, the control section decodes the command field of the request packet, and instructs the memory section to execute writing access or reading access to the memory core section or the memory control register section in the memory section according to the result of the decoding.

27. A method as claimed in claim 20, wherein in the case where the device ID field in the request packet designated the memory section, the control section decodes the command field of the request packet, judges whether the memory section can execute writing access or reading access requested by the request packet or not according to the result of the decoding, transmits the judgment result to the packet-type memory/coprocessor bus as the acknowledge packet, and instructs the memory section to execute the writing access or the reading access to the memory core section or the memory control register section in the memory section if the memory section has been judged to be able to execute the access.

28. A method as claimed in claim 20, wherein in the case where the device ID field in the request packet designated one of the coprocessor sections, the control section decodes the command field of the request packet, and instructs the designated coprocessor section to execute writing access or reading access to the operation control register section in the coprocessor section according to the result of the decoding.

29. A method as claimed in claim 20, wherein in the case where the device ID field in the request packet designated one of the coprocessor sections, the control section decodes the command field of the request packet, judges whether the designated coprocessor section can execute writing access or reading access requested by the request packet or not according to the result of the decoding, transmits the judgment result to the packet-type memory/coprocessor bus as the acknowledge packet, and instructs the designated coprocessor section to execute the writing access or the reading access to the operation control register section in the coprocessor section if the coprocessor section has been judged to be able to execute the access.

30. A method as claimed in claim 20, wherein:

in the case where the device ID field in the request packet designated the memory section, the control section decodes the command field of the request packet, and instructs the memory section to execute writing access or reading access to the memory core section or the memory control register section in the memory section according to the result of the decoding, and

in the case where the device ID field in the request packet designated one of the coprocessor sections, the control section decodes the command field of the request packet, judges whether the designated coprocessor section can execute writing access or reading access requested by the request packet or not according to the result of the decoding, transmits the judgment result to the packet-type memory/coprocessor bus as the acknowledge packet, and instructs the designated coprocessor section to execute the writing access or the reading access to the operation control register section in the coprocessor section if the coprocessor section has been judged to be able to execute the access.

31. A method as claimed in claim 20, wherein:

in the case where the device ID field in the request packet designated the memory section, the control section decodes the command field of the request packet, and instructs the memory section to execute writing access or reading access to the memory core section or the memory control register section in the memory section according to the result of the decoding, and

in the case where the device ID field in the request packet designated one of the coprocessor sections, the control section decodes the command field of the request packet, and then,

if the decoded command field instructed writing access to the operation control register section, the control section judges whether the designated coprocessor section can execute the writing access or not, transmits the judgment result to the packet-type memory/coprocessor bus as the acknowledge packet, and instructs the designated coprocessor section to execute the writing access to the operation control register section in the coprocessor section if the coprocessor section has been judged to be able to execute the access, and

if the decoded command field instructed reading access to the operation control register section, the control section instructs the designated coprocessor section to execute the reading access to the operation control register section in the coprocessor section.

32. A method as claimed in claim 26, wherein in the execution of the writing access to the memory core section, the memory section receives write data which has been included in the write data packet which the control section received from the packet-type memory/coprocessor bus via the interface section, and writes the write data into the memory core section using a memory address which is designated by the parameter field of the request packet.

33. A method as claimed in claim 27, wherein in the execution of the writing access to the memory core section, the memory section receives write data which has been included in the write data packet which the control section received from the packet-type memory/coprocessor bus via the interface section, and writes the write data into the memory core section using a memory address which is designated by the parameter field of the request packet.

34. A method as claimed in claim 30, wherein in the execution of the writing access to the memory core section, the memory section receives write data which has been included in the write data packet which the control section received from the packet-type memory/coprocessor bus via the interface section, and writes the write data into the memory core section using a memory address which is designated by the parameter field of the request packet.

35. A method as claimed in claim 31, wherein in the execution of the writing access to the memory core section, the memory section receives write data which has been included in the write data packet which the control section received from the packet-type memory/coprocessor bus via the interface section, and writes the write data into the memory core section using a memory address which is designated by the parameter field of the request packet.

36. A method as claimed in claim 26, wherein in the execution of the writing access to the memory control register section, the memory section receives write data which has been included in the write data packet which the control section received from the packet-type memory/coprocessor bus via the interface section, and writes the write data into the memory control register which is designated by the parameter field of the request packet.

37. A method as claimed in claim 27, wherein in the execution of the writing access to the memory control register section, the memory section receives write data which has been included in the write data packet which the control section received from the packet-type memory/coprocessor bus via the interface section, and writes the write data into the memory control register which is designated by the parameter field of the request packet.

38. A method as claimed in claim 30, wherein in the execution of the writing access to the memory control register section, the memory section receives write data which has been included in the write data packet which the control section received from the packet-type memory/coprocessor bus via the interface section, and writes the write data into the memory control register which is designated by the parameter field of the request packet.

39. A method as claimed in claim 31, wherein in the execution of the writing access to the memory control register section, the memory section receives write data which has been included in the write data packet which the control section received from the packet-type memory/coprocessor bus via the interface section, and writes the write data into the memory control register which is designated by the parameter field of the request packet.

40. A method as claimed in claim 26, wherein in the execution of the writing access to the memory control register section, the memory section receives write data which has been included in part of the parameter field of the request packet from the control section, and writes the write data into the memory control register which is designated by part of the parameter field of the request packet.

41. A method as claimed in claim 27, wherein in the execution of the writing access to the memory control register section, the memory section receives write data which has been included in part of the parameter field of the request packet from the control section, and writes the write data into the memory control register which is designated by part of the parameter field of the request packet.

42. A method as claimed in claim 30, wherein in the execution of the writing access to the memory control register section, the memory section receives write data which has been included in part of the parameter field of the request packet from the control section, and writes the write data into the memory control register which is designated by part of the parameter field of the request packet.

43. A method as claimed in claim 31, wherein in the execution of the writing access to the memory control register section, the memory section receives write data which has been included in part of the parameter field of the request packet from the control section, and writes the write data into the memory control register which is designated by part of the parameter field of the request packet.

44. A method as claimed in claim 26, wherein in the execution of the reading access to the memory core section or the memory control register section, the memory section reads data out of the memory core section or the memory control register section according to the designation by the parameter field in the request packet and supplies the data to the control section, and the control section assembles the read data packet including the data, and the interface section transmits the read data packet to the packet-type memory/coprocessor bus via the external I/O terminal.

45. A method as claimed in claim 27, wherein in the execution of the reading access to the memory core section or the memory control register section, the memory section reads data out of the memory core section or the memory control register section according to the designation by the parameter field in the request packet and supplies the data to the control section, and the control section assembles the read data packet including the data, and the interface section transmits the read data packet to the packet-type memory/coprocessor bus via the external I/O terminal.

46. A method as claimed in claim 30, wherein in the execution of the reading access to the memory core section or the memory control register section, the memory section reads data out of the memory core section or the memory control register section according to the designation by the parameter field in the request packet and supplies the data to the control section, and the control section assembles the read data packet including the data, and the interface section transmits the read data packet to the packet-type memory/coprocessor bus via the external I/O terminal.

47. A method as claimed in claim 31, wherein in the execution of the reading access to the memory core section or the memory control register section, the memory section reads data out of the memory core section or the memory control register section according to the designation by the parameter field in the request packet and supplies the data to the control section, and the control section assembles the read data packet including the data, and the interface section transmits the read data packet to the packet-type memory/coprocessor bus via the external I/O terminal.

48. A method as claimed in claim 28, wherein in the execution of the writing access to the operation control register section, the coprocessor section receives write data which has been included in the write data packet which the control section received from the packet-type memory/coprocessor bus via the interface section, and writes the write data into the operation control register which is designated by the parameter field of the request packet.

49. A method as claimed in claim 29, wherein in the execution of the writing access to the operation control register section, the coprocessor section receives write data which has been included in the write data packet which the control section received from the packet-type memory/coprocessor bus via the interface section, and writes the write data into the operation control register which is designated by the parameter field of the request packet.

50. A method as claimed in claim 30, wherein in the execution of the writing access to the operation control register section, the coprocessor section receives write data which has been included in the write data packet which the control section received from the packet-type memory/coprocessor bus via the interface section, and writes the write data into the operation control register which is designated by the parameter field of the request packet.

51. A method as claimed in claim 31, wherein in the execution of the writing access to the operation control register section, the coprocessor section receives write data which has been included in the write data packet which the control section received from the packet-type memory/coprocessor bus via the interface section, and writes the write data into the operation control register which is designated by the parameter field of the request packet.

52. A method as claimed in claim 28, wherein in the execution of the writing access to the operation control register section, the coprocessor section receives write data which has been included in part of the parameter field of the request packet from the control section, and writes the write data into the operation control register which is designated by part of the parameter field of the request packet.

53. A method as claimed in claim 29, wherein in the execution of the writing access to the operation control register section, the coprocessor section receives write data which has been included in part of the parameter field of the request packet from the control section, and writes the write data into the operation control register which is designated by part of the parameter field of the request packet.

54. A method as claimed in claim 30, wherein in the execution of the writing access to the operation control register section, the coprocessor section receives write data which has been included in part of the parameter field of the request packet from the control section, and writes the write data into the operation control register which is designated by part of the parameter field of the request packet.

55. A method as claimed in claim 31, wherein in the execution of the writing access to the operation control register section, the coprocessor section receives write data which has been included in part of the parameter field of the request packet from the control section, and writes the write data into the operation control register which is designated by part of the parameter field of the request packet.

56. A method as claimed in claim 28, wherein in the execution of the reading access to the operation control register section, the coprocessor section reads data out of the operation control register which is designated by the parameter field of the request packet and supplies the data to the control section, and the control section assembles the read data packet including the data, and the interface section transmits the read data packet to the packet-type memory/coprocessor bus via the external I/O terminal.

57. A method as claimed in claim 29, wherein in the execution of the reading access to the operation control register section, the coprocessor section reads data out of the operation control register which is designated by the parameter field of the request packet and supplies the data to the control section, and the control section assembles the read data packet including the data, and the interface section transmits the read data packet to the packet-type memory/coprocessor bus via the external I/O terminal.

58. A method as claimed in claim 30, wherein in the execution of the reading access to the operation control register section, the coprocessor section reads data out of the operation control register which is designated by the parameter field of the request packet and supplies the data to the control section, and the control section assembles the read data packet including the data, and the interface section transmits the read data packet to the packet-type memory/coprocessor bus via the external I/O terminal.

59. A method as claimed in claim 31, wherein in the execution of the reading access to the operation control register section, the coprocessor section reads data out of the operation control register which is designated by the parameter field of the request packet and supplies the data to the control section, and the control section assembles the read data packet including the data, and the interface section transmits the read data packet to the packet-type memory/coprocessor bus via the external I/O terminal.

60. A method as claimed in claim 31, wherein:

in the reading access to the memory core section, the memory control register section or the operation control register section, the coprocessor-integrated packet-type memory LSI transmits the read data packet to the packet-type memory/coprocessor bus with predetermined bus timing after the reception of the request packet, and

in the writing access to the operation control register section, the coprocessor-integrated packet-type memory LSI transmits the acknowledge packet to the packet-type memory/coprocessor bus with the same predetermined bus timing after the reception of the request packet.

61. A method as claimed in claim 28, wherein an operation start register is provided in the operation control register section so that the coprocessor section can refer to the operation start register when the coprocessor section starts execution of an arithmetic logic operation, and in the case where writing access to the operation start register is designated by the command field and the parameter field in the request packet, write data included in the parameter field of the request packet or write data included in the write data packet is used as a program pointer indicating an address of the first instruction in an arithmetic logic operation program to be executed, and the coprocessor section starts the execution of the arithmetic logic operation using the program pointer when the program pointer is written into the operation start register.

62. A method as claimed in claim 29, wherein an operation start register is provided in the operation control register section so that the coprocessor section can refer to the operation start register when the coprocessor section starts execution of an arithmetic logic operation, and in the case where writing access to the operation start register is designated by the command field and the parameter field in the request packet, write data included in the parameter field of the request packet or write data included in the write data packet is used as a program pointer indicating an address of the first instruction in an arithmetic logic operation program to be executed, and the coprocessor section starts the execution of the arithmetic logic operation using the program pointer when the program pointer is written into the operation start register.

63. A method as claimed in claim 30, wherein an operation start register is provided in the operation control register section so that the coprocessor section can refer to the operation start register when the coprocessor section starts execution of an arithmetic logic operation, and in the case where writing access to the operation start register is designated by the command field and the parameter field in the request packet, write data included in the parameter field of the request packet or write data included in the write data packet is used as a program pointer indicating an address of the first instruction in an arithmetic logic operation program to be executed, and the coprocessor section starts the execution of the arithmetic logic operation using the program pointer when the program pointer is written into the operation start register.

64. A method as claimed in claim 31, wherein an operation start register is provided in the operation control register section so that the coprocessor section can refer to the operation start register when the coprocessor section starts execution of an arithmetic logic operation, and in the case where writing access to the operation start register is designated by the command field and the parameter field in the request packet, write data included in the parameter field of the request packet or write data included in the write data packet is used as a program pointer indicating an address of the first instruction in an arithmetic logic operation program to be executed, and the coprocessor section starts the execution of the arithmetic logic operation using the program pointer when the program pointer is written into the operation start register.

65. A method as claimed in claim 61, wherein in the case where writing access to the operation start register is designated by the request packet, information indicating whether the coprocessor section can execute the designated arithmetic logic operation or not is transmitted as the acknowledge packet to the packet-type memory/coprocessor bus and the arithmetic logic operation is executed by the coprocessor section only when the execution of the designated arithmetic logic operation by the coprocessor section is possible.

66. A method as claimed in claim 62, wherein in the case where writing access to the operation start register is designated by the request packet, information indicating whether the coprocessor section can execute the designated arithmetic logic operation or not is transmitted as the acknowledge packet to the packet-type memory/coprocessor bus and the arithmetic logic operation is executed by the coprocessor section only when the execution of the designated arithmetic logic operation by the coprocessor section is possible.

67. A method as claimed in claim 63, wherein in the case where writing access to the operation start register is designated by the request packet, information indicating whether the coprocessor section can execute the designated arithmetic logic operation or not is transmitted as the acknowledge packet to the packet-type memory/coprocessor bus and the arithmetic logic operation is executed by the coprocessor section only when the execution of the designated arithmetic logic operation by the coprocessor section is possible.

68. A method as claimed in claim 64, wherein in the case where writing access to the operation start register is designated by the request packet, information indicating whether the coprocessor section can execute the designated arithmetic logic operation or not is transmitted as the acknowledge packet to the packet-type memory/coprocessor bus and the arithmetic logic operation is executed by the coprocessor section only when the execution of the designated arithmetic logic operation by the coprocessor section is possible.

69. A method as claimed in claim 56, wherein an operation result register is provided as one of the operation control registers so that the coprocessor section can write the result of an arithmetic logic operation into the operation result register, and in the case where reading access to the operation result register is designated by the command field and the parameter field in the request packet, data stored in the operation result register is read out and assembled as the read data packet and the read data packet is transmitted to the packet-type memory/coprocessor bus.

70. A method as claimed in claim 57, wherein an operation result register is provided as one of the operation control registers so that the coprocessor section can write the result of an arithmetic logic operation into the operation result register, and in the case where reading access to the operation result register is designated by the command field and the parameter field in the request packet, data stored in the operation result register is read out and assembled as the read data packet and the read data packet is transmitted to the packet-type memory/coprocessor bus.

71. A method as claimed in claim 58, wherein an operation result register is provided as one of the operation control registers so that the coprocessor section can write the result of an arithmetic logic operation into the operation result register, and in the case where reading access to the operation result register is designated by the command field and the parameter field in the request packet, data stored in the operation result register is read out and assembled as the read data packet and the read data packet is transmitted to the packet-type memory/coprocessor bus.

72. A method as claimed in claim 59, wherein an operation result register is provided as one of the operation control registers so that the coprocessor section can write the result of an arithmetic logic operation into the operation result register, and in the case where reading access to the operation result register is designated by the command field and the parameter field in the request packet, data stored in the operation result register is read out and assembled as the read data packet and the read data packet is transmitted to the packet-type memory/coprocessor bus.

73. A method as claimed in claim 69, wherein in the case where reading access to the operation result register is designated by the request packet, information indicating whether the result of the arithmetic logic operation has already been written in the designated operation result register or not is transmitted as the acknowledge packet to the packet-type memory/coprocessor bus and the reading access to the operation result register is executed only when the result of the arithmetic logic operation has already been written in the operation result register.

74. A method as claimed in claim 70, wherein in the case where reading access to the operation result register is designated by the request packet, information indicating whether the result of the arithmetic logic operation has already been written in the designated operation result register or not is transmitted as the acknowledge packet to the packet-type memory/coprocessor bus and the reading access to the operation result register is executed only when the result of the arithmetic logic operation has already been written in the operation result register.

75. A method as claimed in claim 71, wherein in the case where reading access to the operation result register is designated by the request packet, information indicating whether the result of the arithmetic logic operation has already been written in the designated operation result register or not is transmitted as the acknowledge packet to the packet-type memory/coprocessor bus and the reading access to the operation result register is executed only when the result of the arithmetic logic operation has already been written in the operation result register.

76. A method as claimed in claim 72, wherein in the case where reading access to the operation result register is designated by the request packet, information indicating whether the result of the arithmetic logic operation has already been written in the designated operation result register or not is transmitted as the acknowledge packet to the packet-type memory/coprocessor bus and the reading access to the operation result register is executed only when the result of the arithmetic logic operation has already been written in the operation result register.

77. A method as claimed in claim 69, wherein in the case where reading access to the operation result register is designated by the request packet, information indicating whether the result of the arithmetic logic operation has already been written in the designated operation result register or not is transmitted included in the read data packet to the packet-type memory/coprocessor bus.

78. A method as claimed in claim 70, wherein in the case where reading access to the operation result register is designated by the request packet, information indicating whether the result of the arithmetic logic operation has already been written in the designated operation result register or not is transmitted included in the read data packet to the packet-type memory/coprocessor bus.

79. A method as claimed in claim 71, wherein in the case where reading access to the operation result register is designated by the request packet, information indicating whether the result of the arithmetic logic operation has already been written in the designated operation result register or not is transmitted included in the read data packet to the packet-type memory/coprocessor bus.

80. A method as claimed in claim 72, wherein in the case where reading access to the operation result register is designated by the request packet, information indicating whether the result of the arithmetic logic operation has already been written in the designated operation result register or not is transmitted included in the read data packet to the packet-type memory/coprocessor bus.

81. A method as claimed in claim 61, wherein the coprocessor section starts the execution of the arithmetic logic operation according to the writing access to the operation start register, after parameters which are needed by the coprocessor section for executing the arithmetic logic operation have been written into a desired number of the operation control registers by means of the writing access to the operation control registers, and the coprocessor section carries out the arithmetic logic operation referring to the parameters stored in the operation control registers.

82. A method as claimed in claim 62, wherein the coprocessor section starts the execution of the arithmetic logic operation according to the writing access to the operation start register, after parameters which are needed by the coprocessor section for executing the arithmetic logic operation have been written into a desired number of the operation control registers by means of the writing access to the operation control registers, and the coprocessor section carries out the arithmetic logic operation referring to the parameters stored in the operation control registers.

83. A method as claimed in claim 63, wherein the coprocessor section starts the execution of the arithmetic logic operation according to the writing access to the operation start register, after parameters which are needed by the coprocessor section for executing the arithmetic logic operation have been written into a desired number of the operation control registers by means of the writing access to the operation control registers, and the coprocessor section carries out the arithmetic logic operation referring to the parameters stored in the operation control registers.

84. A method as claimed in claim 64, wherein the coprocessor section starts the execution of the arithmetic logic operation according to the writing access to the operation start register, after parameters which are needed by the coprocessor section for executing the arithmetic logic operation have been written into a desired number of the operation control registers by means of the writing access to the operation control registers, and the coprocessor section carries out the arithmetic logic operation referring to the parameters stored in the operation control registers.

85. A method as claimed in claim 69, wherein a desired number of the operation control registers are also used for storing part of the result of the arithmetic logic operation when the result can not be accommodated in the operation result register, and the result is read out from the coprocessor section by means of reading access to the operation control registers after part of the result is successfully read out by means of the reading access to the operation result register.

86. A method as claimed in claim 70, wherein a desired number of the operation control registers are also used for storing part of the result of the arithmetic logic operation when the result can not be accommodated in the operation result register, and the result is read out from the coprocessor section by means of reading access to the operation control registers after part of the result is successfully read out by means of the reading access to the operation result register.

87. A method as claimed in claim 71, wherein a desired number of the operation control registers are also used for storing part of the result of the arithmetic logic operation when the result can not be accommodated in the operation result register, and the result is read out from the coprocessor section by means of reading access to the operation control registers after part of the result is successfully read out by means of the reading access to the operation result register.

88. A method as claimed in claim 72, wherein a desired number of the operation control registers are also used for storing part of the result of the arithmetic logic operation when the result can not be accommodated in the operation result register, and the result is read out from the coprocessor section by means of reading access to the operation control registers after part of the result is successfully read out by means of the reading access to the operation result register.

89. A method as claimed in claim 56, wherein a desired number of the operation control registers are used for storing intermediate data which are generated during execution of an arithmetic logic operation by the coprocessor section, and in the case where reading access to one of the operation control registers storing the intermediate data is designated by the command field and the parameter field in the request packet, the intermediate data stored in the operation control register is read out and assembled as the read data packet and the read data packet is transmitted to the packet-type memory/coprocessor bus.

90. A method as claimed in claim 57, wherein a desired number of the operation control registers are used for storing intermediate data which are generated during execution of an arithmetic logic operation by the coprocessor section, and in the case where reading access to one of the operation control registers storing the intermediate data is designated by the command field and the parameter field in the request packet, the intermediate data stored in the operation control register is read out and assembled as the read data packet and the read data packet is transmitted to the packet-type memory/coprocessor bus.

91. A method as claimed in claim 58, wherein a desired number of the operation control registers are used for storing intermediate data which are generated during execution of an arithmetic logic operation by the coprocessor section, and in the case where reading access to one of the operation control registers storing the intermediate data is designated by the command field and the parameter field in the request packet, the intermediate data stored in the operation control register is read out and assembled as the read data packet and the read data packet is transmitted to the packet-type memory/coprocessor bus.

92. A method as claimed in claim 59, wherein a desired number of the operation control registers are used for storing intermediate data which are generated during execution of an arithmetic logic operation by the coprocessor section, and in the case where reading access to one of the operation control registers storing the intermediate data is designated by the command field and the parameter field in the request packet, the intermediate data stored in the operation control register is read out and assembled as the read data packet and the read data packet is transmitted to the packet-type memory/coprocessor bus.

93. A coprocessor-integrated packet-type memory LSI as claimed in claim 21, wherein:

the coprocessor-integrated packet-type memory LSI is provided with an external select-in terminal and an external select-out terminal,

each of the memory section and the coprocessor sections is provided with an internal select-in terminal and an internal select-out terminal,

a memory section/coprocessor section chain is formed by connecting the internal select-out terminals with corresponding internal select-in terminals and connecting all of the memory section and the coprocessor sections into a chain,

the external select-in terminal of the coprocessor-integrated packet-type memory LSI is connected to the internal select-in terminal of the first block of the memory section/coprocessor section chain, and

the internal select-out terminal of the final block of the memory section/coprocessor section chain is connected to the external select-out terminal of the coprocessor-integrated packet-type memory LSI.

94. A method for controlling the coprocessor-integrated packet-type memory LSI of claim 93, in which:

as an initialization process, the memory device ID and the coprocessor device IDs of the memory section and the coprocessor sections in the coprocessor-integrated packet-type memory LSI are set at a predetermined initial value and all of the internal select-out terminals of the memory section and the coprocessor sections are set at the logical value ‘

0’

, and

after the initialization process, each of the memory section and the coprocessor sections whose memory device ID and the coprocessor device IDs have been set at the initial value ignores writing access thereto and keeps on outputting the logical value ‘

0’

from its internal select-out terminal as long as the logical values ‘

0’

is supplied to its internal select-in terminal, and

each of the memory section and the coprocessor sections accepts the writing access thereto and outputs the logical value ‘

1’

from its internal select-out terminal as long as the logical value ‘

1’

is supplied to its internal select-in terminal, and thereby the memory device ID or the coprocessor device ID designated by the parameter field of the request packet is written into the memory device ID register or the coprocessor device ID register thereof according to the writing access thereto.

95. A packet-type memory/coprocessor bus as claimed in claim 4, wherein:

a coprocessor-integrated packet-type memory LSI chain is formed by connecting a desired number of the coprocessor-integrated packet-type memory LSIs of claim 93 into a chain by connecting the external select-out terminals and corresponding external select-in terminals,

the bus master is provided with an external select-in terminal and an external select-out terminal,

the external select-out terminal of the bus master is connected to the external select-in terminal of the first coprocessor-integrated packet-type memory LSI in the coprocessor-integrated packet-type memory LSI chain, and

the external select-out terminal of the final coprocessor-integrated packet-type memory LSI in the coprocessor-integrated packet-type memory LSI chain is connected to the external select-in terminal of the bus master.

96. A packet-type memory/coprocessor bus as claimed in claim 5, wherein:

a coprocessor-integrated packet-type memory LSI chain is formed by connecting a desired number of the coprocessor-integrated packet-type memory LSIs of claim 93 into a chain by connecting the external select-out terminals and corresponding external select-in terminals,

the bus master is provided with an external select-in terminal and an external select-out terminal,

the external select-out terminal of the bus master is connected to the external select-in terminal of the first coprocessor-integrated packet-type memory LSI in the coprocessor-integrated packet-type memory LSI chain, and

the external select-out terminal of the final coprocessor-integrated packet-type memory LSI in the coprocessor-integrated packet-type memory LSI chain is connected to the external select-in terminal of the bus master.

97. A method for controlling the packet-type memory/coprocessor bus of claim 95 or 96, in which:

as an initialization process, the memory device IDs and the coprocessor device IDs of all of the memory sections and the coprocessor sections in all of the coprocessor-integrated packet-type memory LSI connected to the packet-type memory/coprocessor bus are set at a predetermined initial value and all of the internal select-out terminals of the memory sections and the coprocessor sections are set at the logical value ‘

0’

, and

after the initialization process, the bus master varies the logical value of its external select-out terminal from ‘

0’

to ‘

1’ and

transmits a request packet designating the initial value in the device ID field of the request packet and designating a new memory device ID or a new coprocessor device ID in the parameter field of the request packet, thereby the new memory device ID or the new coprocessor device ID is assigned to the first block in the memory section/coprocessor section chain in the first coprocessor-integrated packet-type memory LSI in the coprocessor-integrated packet-type memory LSI chain, and

thereafter, the bus master repeats transmitting request packets designating the initial value in the device ID field of the request packet and designating a new memory device ID or a new coprocessor device ID in the parameter field of the request packet, thereby specific and unique memory device IDs and coprocessor device IDs are assigned to the memory sections and the coprocessor sections in the coprocessor-integrated packet-type memory LSI chain one after another according to the transmission of the logical value ‘

1’

through the blocks in the coprocessor-integrated packet-type memory LSI chain.

98. A coprocessor-integrated packet-type memory LSI as claimed in claim 2, wherein:

the memory section includes a device definition register as one of the memory control registers, for prestoring device definition information to be used for discriminating between a memory section and a coprocessor section, and

each of the coprocessor sections includes a device definition register as one of the operation control registers, for prestoring device definition information to be used for discriminating between a memory section and a coprocessor section.

99. A method for controlling the coprocessor-integrated packet-type memory LSI of claim 98, in which the bus master checks whether a particular device ID has been assigned to a memory section or a coprocessor section, by obtaining the device definition information by executing reading access designating the particular device ID to the device definition register in the memory control register section or the operation control register section.

100. A method as claimed in claim 99, wherein request packets which are the same except for designation of the device ID field are used by the bus master for the reading accesses to the device definition registers, regardless of whether the destination of the reading access is in a memory section or in a coprocessor section.

101. A coprocessor-integrated packet-type memory LSI as claimed in claim 2, wherein the operation control register section includes a function definition register as one of the operation control registers, for prestoring function definition code which classifies the arithmetic logic operation functions of the coprocessor section.

102. A method for controlling the coprocessor-integrated packet-type memory LSI of claim 101, in which the bus master checks arithmetic logic operation functions of a coprocessor section which corresponds to a particular device ID, by obtaining the function definition code by executing reading access designating the particular device ID to the function definition register in the operation control register section.