Integrated circuit analytical imaging technique employing a backside surface fill layer

• US 6,338,974 B1
• Filed: 07/31/2000
• Issued: 01/15/2002
• Est. Priority Date: 07/31/2000
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Strnad, Richard J.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Dang, Phuc T.
• Application Number:
  US09/629,767
• Time in Patent Office: 533 Days
• Field of Search: 438/14, 438/16, 438/17, 438/57, 438/66, 438/68, 438/72, 438/108, 438/4, 438/110, 438/113, 438/114, 438/122
• US Class Current: 438/16
• CPC Class Codes: G01R 31/311 of integrated circuits G01R31/31728 takes precedence

Abstract

An integrated circuit (IC) analytical imaging process that does not require a mirror-like semiconductor substrate backside surface and that is simple, fast and inexpensive. The process includes steps of first providing a semiconductor device structure with a semiconductor substrate and an IC formed in and on the upper surface of the semiconductor substrate, followed by thinning of the semiconductor substrate by removing semiconductor material from its lower surface. This thinning step creates a thinned semiconductor substrate with a backside surface with a roughness due to the presence of peaks and valleys. A backside surface fill material (e.g., water, optical grade oil or optical grade epoxy) is then applied to the backside surface of the thinned semiconductor substrate. The application of the backside surface fill material creates a backside surface fill material layer that at least partially fills the valleys. An analytical imaging technique (e.g., photon emission microscopy or voltage contrast analysis) is subsequently performed by collecting radiation emitted through the backside surface. The presence of a backside surface fill material layer, which at least partially fills the valleys of the backside surface, improves the transmissivity and efficiency of radiation emission through the backside surface.

Claims

1. An integrated circuit analytical imaging method, the method comprising:

providing a semiconductor device structure that includes a semiconductor having an integrated circuit formed in and on an upper surface of the semiconductor substrate;

thinning the semiconductor substrate by removing semiconductor material from a lower surface of the semiconductor substrate, thereby creating a thinned semiconductor substrate having a backside surface, the backside surface having a plurality of peaks and a plurality of valleys formed therein;

forming a backside surface fill material layer on the backside surface of the thinned semiconductor substrate, to at least partially fill the plurality of valleys; and

performing an analytical imaging technique by collecting radiation emitted through the backside surface.

2. The method of claim 1, and wherein the forming step comprises applying a backside surface fill material that is a liquid.

3. The method of claim 1, and wherein the forming step comprises applying water as the backside surface fill material.

4. The method of claim 1, and wherein the forming step comprises applying an optical grade epoxy as the backside surface fill material.

5. The method of claim 1, and wherein the forming step comprises applying an organic material as the backside surface fill material.

6. The method of claim 1, and wherein the forming step comprises applying an optical grade glass as the backside surface fill material.

7. The method of claim 1, and wherein the semiconductor substrate comprises of silicon.

8. The method of claim 1, and wherein the performing step includes performing a voltage contrast analytical imaging technique.

9. The method of claim 1, and wherein the performing step includes performing a photon emission microscopic analytical imaging technique.

10. The method of claim 1, and wherein the performing step includes performing a photon emission microscopic analytical imaging technique using an immersion objective lens, during which the immersion objective lens is immersed in the backside surface fill material layer.

11. The method of claim 1, and wherein the forming step creates a backside surface fill material layer having a planar exposed surface.

12. An integrated circuit analytical imaging method, the method comprising:

providing a semiconductor device structure that includes a semiconductor substrate having an integrated circuit formed in and on an upper surface of the semiconductor substrate;

thinning the semiconductor substrate by removing semiconductor material from a lower surface of the semiconductor substrate, thereby creating a thinned semiconductor substrate having a backside surface, the backside surface having a plurality of peaks and a plurality of valleys formed therein;

applying an optical grade oil to the backside surface of the thinned semiconductor substrate, thereby creating optical grade oil layer that at least partially fills the plurality of valleys; and

performing an analytical imaging technique by collecting radiation emitted through the backside surface.

13. An integrated circuit analytical imaging method, the method comprising:

providing a semiconductor device structure that includes a semiconductor substrate having an integrated circuit formed in and on an upper surface of the semiconductor substrate;

thinning the semiconductor substrate by removing semiconductor material from a lower surface of the semiconductor substrate, thereby creating a thinned semiconductor substrate having a backside surface, the backside surface having a plurality of peaks and a plurality of valleys formed therein;

applying a silicon rubber to the backside surface of the thinned semiconductor substrate, thereby creating a silicon rubber layer that at least partially fills the plurality of valleys; and

performing an analytical imaging technique by collecting radiation emitted through the backside surface.