High voltage device and method for fabricating the same

• US 6,339,243 B1
• Filed: 03/02/2000
• Issued: 01/15/2002
• Est. Priority Date: 03/04/1999
• Status: Expired due to Term

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: Jin, Jun Hee, Kwon, Oh Kyong
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US09/517,303
• Time in Patent Office: 684 Days
• Field of Search: 257/341, 257/378, 257/339, 257/347, 257/370, 257/401, 257/507, 257/514, 438/202, 438/219, 438/234, 438/694
• US Class Current: 257/341
• CPC Class Codes: H01L 29/66325 controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
• CPC Class Codes: H01L 29/7394 on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate H01L29/7398 takes precedence

Abstract

The disclosed high voltage device includes a semiconductor substrate, and a first semiconductor layer formed between an underlying first insulating layer and an overlying second insulating layer buried within the semiconductor substrate. The high voltage device includes first and second drift regions formed over the second insulating layer in the semiconductor substrate and spaced apart from each other, an emitter impurity region formed in the first drift region, and a collector impurity region formed in the second drift region. The high voltage device further includes a second semiconductor layer adjacent to and insulated from the collector impurity region, and connected to the first semiconductor layer, and a third semiconductor layer adjacent to and insulated from the emitter impurity region, and connected to the first semiconductor layer. The high voltage device includes a gate electrode formed over and insulated from the first drift region adjacent to the emitter impurity region; an emitter electrode electrically connected to the emitter impurity region and the third semiconductor layer, the emitter electrode being insulated from the gate electrode; a collector electrode electrically connected to the collector impurity region and the second semiconductor layer; and, a field plate electrode formed between the collector electrode and the emitter electrode, and insulated from the gate electrode.

Claims

1. A high voltage device comprising:

a semiconductor substrate;

a first semiconductor layer formed between an underlying first insulating layer and an overlying second insulating layer buried within the semiconductor substrate;

first and second drift regions formed over the second insulating layer in the semiconductor substrate and spaced apart from each other;

an emitter impurity region formed in the first drift region;

a collector impurity region formed in the second drift region;

a second semiconductor layer adjacent to and insulated from the collector impurity region, and connected to the first semiconductor layer;

a third semiconductor layer adjacent to and insulated from the emitter impurity region, and connected to the first semiconductor layer;

a gate electrode formed over and insulated from the first drift region adjacent to the emitter impurity region;

an emitter electrode electrically connected to the emitter impurity region and the third semiconductor layer, the emitter electrode being insulated from the gate electrode;

a collector electrode electrically connected to the collector impurity region and the second semiconductor layer; and

a field plate electrode formed between the collector electrode and the emitter electrode, and insulated from the gate electrode.

2. The high voltage device as claimed in claim 1, further comprising a double diffusion region formed in the first drift region and having a same conduction type as the first drift region,

wherein the emitter impurity region is formed in the double diffusion region.

3. The high voltage device as claimed in claim 1, further comprising a buffer region formed in the second drift region and having a same conduction type as the second drift region,

wherein the collector impurity region is formed in the buffer region.

4. The high voltage device as claimed in claim 1, wherein the second semiconductor layer functions as an anode electrode of a diode, and the third semiconductor layer functions as a cathode electrode of the diode.

5. The high voltage device as claimed in claim 1, wherein

the substrate, first drift region, and third semiconductor layer are of a P-conduction type, and

the first semiconductor layer, second drift region, and second semiconductor layer are of an N-conduction type.

6. The high voltage device as claimed in claim 1, wherein the first, second and third semiconductor layers are formed of polysilicon.

7. A high voltage device as claimed in claim 1, further comprising a quasi LDD region in the first drift region at one side of the gate electrode opposite to the emitter impurity region.

8. A high voltage device as claimed in claim 1, wherein the gate electrode, the emitter electrode, and collector electrode form an IGBT device.

9. A high voltage device comprising:

a semiconductor substrate;

a first semiconductor layer formed between an underlying first insulating layer and an overlying second insulating layer buried within the semiconductor substrate;

a third insulating layer surrounding a device isolation region above the second insulating layer in the semiconductor substrate;

a first impurity region formed in the device isolation region;

a second impurity region formed in the device isolation region and spaced apart from the first impurity region;

a second semiconductor layer outside the device isolation region and connected to the first semiconductor layer;

a third semiconductor layer outside the device isolation region and connected to the first semiconductor layer;

a gate electrode over and insulated from the device isolation region and adjacent to the first impurity region;

a fourth insulating layer over the gate electrode and the device isolation region;

a first electrode electrically connected to the first impurity region and the third semiconductor layer; and

a second electrode electrically connected to the second impurity region and the second semiconductor layer.

10. The high voltage device as claimed in claim 9, further comprising a field plate electrode on the fourth insulating layer between the first and second electrodes.

11. The high voltage device as claimed in claim 9, further comprising:

a first drift region in the device isolation region and having a same conduction type as the third semiconductor layer, and

a second drift region in the device isolation region and having a same conduction type as the second semiconductor layer, wherein

the first impurity region is formed in the first drift region, and the second impurity region is formed in the second drift region.

12. The high voltage device as claimed in claim 11, further comprising:

a double diffusion region in the first drift region and having a same conduction type as the first drift region, the first impurity region being formed in the double diffusion region, and

a buffer region in the second drift region and having a same conduction type as the second drift region, the second impurity region being formed in the buffer region.

13. The high voltage device as claimed in claim 9, wherein

the first impurity region is an emitter impurity region,

the second impurity region is a collector impurity region,

the first electrode is an emitter electrode,

the second electrode is a collector electrode, and

the gate, emitter, and collector electrodes form an IGBT device.

14. The high voltage device as claimed in claim 9, wherein

the first impurity region is a source impurity region,

the second impurity region is a drain impurity region,

the first electrode is a source electrode,

the second electrode is a drain electrode, and

the gate, source, and drain electrodes form an MOS transistor.

15. The high voltage device as claimed in claim 9, wherein the third semiconductor layer functions as a cathode electrode of a diode, and the second semiconductor layer functions as an anode electrode of the diode.

16. The high voltage device as claimed in claim 9, wherein

the semiconductor substrate and the third semiconductor layer are of a P-conduction type, and

the first and second semiconductor layers are of an N-conduction type.

17. A method for fabricating a high voltage device, comprising the steps of:

(1) forming a first insulating layer in a first conduction type substrate, a second conduction type first semiconductor layer on the first insulating layer, and a second insulating layer on the second conduction type first semiconductor layer;

(2) dividing a portion of the substrate above the second insulating layer into first and second conduction type drift regions;

(3) selectively removing the first and second conduction type drift regions and surrounding the remaining portions of the first and second conduction type drift regions with a third insulating layer to form a device isolation region;

(4) forming a second conduction type second semiconductor layer and a first conduction type third semiconductor layer outside the device isolation region and each connected to the second conduction type first semiconductor layer;

(5) forming a gate electrode over the first conduction type drift region;

(6) forming an emitter impurity region in the first conduction type drift region adjacent to the gate electrode and a collector impurity region in the second conduction type drift region in the device isolation region; and

(7) forming an emitter electrode, a collector electrode, and a field plate electrode, each being insulated from the gate electrode, wherein the emitter electrode is connected to the emitter impurity region and the first conduction type third semiconductor layer, the collector electrode is connected to the collector impurity region and the second conduction type second semiconductor layer, and the field plate electrode is disposed between the emitter electrode and the collector electrode.

18. The method as claimed in claim 17, further comprising the step of:

forming a first conduction type double diffusion region in the first conduction type drift region and a second conduction type buffer region in the second conduction type drift region in the device isolation region.

19. The method as claimed in claim 18, further comprising the step of forming a quasi LDD region in the double diffusion region, the quasi LDD region being adjacent to one side of the gate electrode opposite to the emitter impurity region.

20. The method as claimed in claim 17, wherein the step (1) includes the steps of,

(1-1) providing a first substrate and a second substrate, both having the first conduction type,

(1-2) forming the first insulating layer on the first substrate, and forming the second conduction type first semiconductor layer on the first insulating layer,

(1-3) forming, the second insulating layer on the second substrate, and

(1-4) bonding the first substrate and the second substrate so that the second insulating layer is bonded to the first semiconductor layer.

21. The method as claimed in claim 17, wherein the second conduction type first semiconductor layer, second conduction type second semiconductor layer, and first conduction type third semiconductor layer form a diode.

22. A method as claimed in claim 17, wherein the step (3) includes the steps of:

(3-1) selectively removing the first and second conduction type drift regions of the substrate to expose surfaces of the second conduction type first semiconductor layer, and

(3-2) forming a third insulating layer surrounding the remaining first and second conduction type drift regions of the substrate.

23. The method as claimed in claim 17, wherein the second conduction type second semiconductor layer and first conduction type third semiconductor layer include polysilicon.

24. A method as claimed in claim 17, wherein the step (4) includes the steps of:

(4-1) forming an undoped polysilicon outside the device isolation region;

(4-2) injecting first conduction type impurity into a portion of the undoped polysilicon adjacent to the first conduction type drift region to form the first conduction type third semiconductor layer; and

(4-3) injecting second conduction type impurity into a portion of the undoped polysilicon adjacent to the second conduction type drift region to form the second conduction type second semiconductor layer.