Device and method for electrically or thermally coupling to the backsides of integrated circuit dice in chip-on-board applications
First Claim
1. A printed circuit board for chip-on-board applications, the printed circuit board comprising:
- a first dielectric layer including a top surface;
a first conductive layer positioned adjacently above the top surface of the first dielectric layer and including an upwardly facing die-mounting surface within a chip-attach area of the first conductive layer for direct conductive attachment to a backside surface of a bare integrated circuit chip to establish at least one of electrical and thermal conduction between the top surface of the first conductive layer and a bare integrated circuit chip;
a second dielectric layer positioned adjacently above the upwardly facing die-mounting surface of the first conductive layer, the second dielectric layer having an aperture therein to further define the chip-attach area of the first conductive layer and to receive a bare integrated circuit chip;
a second conductive layer positioned adjacently below the first dielectric layer, the second conductive layer extending laterally underneath at least the chip-attach area of the first conductive layer, the second conductive layer vertically insulated from direct electrical communication with the first conductive layer;
an insulative substrate positioned adjacently below the second conductive layer; and
a layer of signal traces superimposed on the second dielectric layer in a substantially parallel relationship therewith, at least some of the signal traces of the layer of signal traces including bond pads for electrical connection to a front-side surface of a bare integrated circuit chip.
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Abstract
An inventive printed circuit board for chip-on-board applications has a ground plane that is externally exposed through apertures in any overlying layers in the board so the backside surface of a bare integrated circuit die can be directly attached to the ground plane using a silver-filled epoxy. As a result, heat is conducted away from the die through the ground plane. Also, a substrate bias voltage can be supplied to the backside surface of the die through the ground plane to eliminate the need for an internal substrate bias to the die, and to eliminate the need for a substrate bias voltage bond pad on the front-side surface of the die.
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Citations
42 Claims
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1. A printed circuit board for chip-on-board applications, the printed circuit board comprising:
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a first dielectric layer including a top surface;
a first conductive layer positioned adjacently above the top surface of the first dielectric layer and including an upwardly facing die-mounting surface within a chip-attach area of the first conductive layer for direct conductive attachment to a backside surface of a bare integrated circuit chip to establish at least one of electrical and thermal conduction between the top surface of the first conductive layer and a bare integrated circuit chip;
a second dielectric layer positioned adjacently above the upwardly facing die-mounting surface of the first conductive layer, the second dielectric layer having an aperture therein to further define the chip-attach area of the first conductive layer and to receive a bare integrated circuit chip;
a second conductive layer positioned adjacently below the first dielectric layer, the second conductive layer extending laterally underneath at least the chip-attach area of the first conductive layer, the second conductive layer vertically insulated from direct electrical communication with the first conductive layer;
an insulative substrate positioned adjacently below the second conductive layer; and
a layer of signal traces superimposed on the second dielectric layer in a substantially parallel relationship therewith, at least some of the signal traces of the layer of signal traces including bond pads for electrical connection to a front-side surface of a bare integrated circuit chip. - View Dependent Claims (2, 3, 4)
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5. A multi-chip module comprising:
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a first supporting substrate including an insulative surface;
a first conductive layer positioned adjacently above the insulative surface of the first supporting substrate and including a top surface with a plurality of localized die-attach areas thereon;
a plurality of bare integrated circuit dice, each associated with one of the plurality of die-attach areas, each of the plurality of bare integrated circuit dice including opposing front-side and backside surfaces, the front-side surface of each of the plurality of bare integrated circuit dice including a plurality of bond pads thereon;
a conductive die-attach material interposed between each of the bare integrated circuit dice and each associated localized die-attach area for directly attaching the backside surface of each die to its associated localized die-attach area to establish at least one of electrical and thermal conduction between each die and each of the localized die-attach areas of the top surface of the first conductive layer;
an insulating layer positioned adjacently above the top surface of the first conductive layer, the insulating layer having a plurality of apertures therein, each aperture in substantial registry with one of the attached bare integrated circuit dice;
a second conductive layer positioned adjacently below the first supporting substrate, the second conductive layer extending laterally underneath at least the plurality of localized die-attach areas of the first conductive layer, the second conductive layer vertically insulated from direct electrical communication with the first conductive layer by the first supporting substrate;
a second, insulative supporting substrate positioned adjacently below the second conductive layer;
a signal layer connected to the insulating layer in a substantially parallel relationship therewith, the signal layer having a plurality of conductor-devoid areas therein, each conductor-devoid area in substantial registry with one of the attached bare integrated circuit dice, the signal layer including a plurality of terminals; and
a plurality of conductors coupling the plurality of terminals of the signal layer to the plurality of bond pads on the front-side surfaces of the bare integrated circuit dice. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. An electronic device comprising:
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a first supporting substrate including an insulative surface;
a first conductive layer positioned adjacently above the insulative surface of the first supporting substrate and including a top surface with a localized die-attach area thereon;
a bare integrated circuit die having opposing front-side and backside surfaces, the front-side surface having a plurality of bond pads thereon;
a conductive die-attach material for directly attaching the backside surface of the bare integrated circuit die to the localized die-attach area on the surface of the first conductive layer to establish at least one of electrical and thermal conduction between the backside surface of the bare integrated circuit die and the localized die attach area on the top surface of the first conductive layer;
an insulating layer positioned adjacently above the top surface of the first conductive layer, the insulating layer having an aperture therein in substantial registry with the attached bare integrated circuit die;
a second conductive layer positioned adjacently below the first supporting substrate, the second conductive layer extending laterally underneath at least the localized die-attach area of the first conductive layer, the second conductive layer vertically insulated from direct electrical communication with the first conductive layer;
a second supporting substrate positioned adjacently below the second conductive layer;
a signal layer connected to the insulating layer in a substantially parallel relationship therewith, the signal layer having an aperture therein in substantial registry with the attached bare integrated circuit die, the signal layer including a plurality of terminals; and
a plurality of conductors coupling the plurality of terminals of the signal layer to the plurality of bond pads on the front-side surface of the bare integrated circuit die. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28)
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29. A system for conducting heat away from a bare integrated circuit die, the system comprising:
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a first dielectric layer;
a first thermally conductive layer positioned adjacently above the first dielectric layer, the first thermally conductive layer positioned internally in a printed circuit board, the first thermally conductive layer including a top surface with an externally accessible localized die-attach region;
a second dielectric layer having an aperture in substantial registry with the externally accessible localized die-attach region of the first thermally conductive layer, the second dielectric layer positioned adjacently above the first thermally conductive layer;
a second thermally conductive layer positioned adjacently below the first dielectric layer, the second thermally conductive layer extending laterally underneath at least the externally accessible localized die-attach region of the first thermally conductive layer, the second thermally conductive layer vertically insulated from direct electrical communication with the first thermally conductive layer; and
a thermally conductive die-attach material for directly attaching a backside surface of a bare integrated circuit die to the externally accessible localized die-attach region on the top surface of the first thermally conductive layer to establish thermal conduction between the bare integrated circuit die and the first thermally conductive layer. - View Dependent Claims (30, 31)
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32. A system for supplying a substrate bias voltage to a bare integrated circuit die, the system comprising:
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a substrate bias voltage generator for supplying a substrate bias voltage;
a first electrically conductive layer positioned within a printed circuit board and coupled to the substrate bias voltage generator, the first electrically conductive layer including a top surface with an externally accessible localized die-attach region;
a second electrically conductive layer positioned within a printed circuit board and coupled to the substrate bias voltage generator, the second electrically conductive layer positioned below and extending laterally underneath at least the externally accessible localized die-attach region of the first electrically conductive layer, the second electrically conductive layer vertically insulated from direct electrical communication with the first electrically conductive layer; and
an electrically conductive die-attach material for directly attaching a backside surface of a bare integrated circuit die to the externally accessible localized die-attach region on the top surface of the first electrically conductive layer to conduct the substrate bias voltage from the first electrically conductive layer to the backside surface of the bare integrated circuit die. - View Dependent Claims (33, 34, 35, 36, 37, 38, 39, 40, 41)
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42. A system for supplying a substrate bias voltage to a bare integrated circuit die, the system consisting essentially of:
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a substrate bias voltage generator for supplying the substrate bias voltage;
a first electrically conductive layer positioned internally in a printed circuit board and coupled to the substrate bias voltage generator, the first electrically conductive layer including a top surface with an externally accessible localized die-attach region;
a second electrically conductive layer positioned within a printed circuit board and coupled to the substrate bias voltage generator, the second electrically conductive layer positioned below and extending laterally underneath at least the externally accessible localized die-attach region of the first conductive layer, the second conductive layer vertically insulated from direct electrical communication with the first electrically conductive layer; and
an electrically conductive die-attach material for directly attaching a backside surface of the bare integrated circuit die to the externally accessible localized die-attach region on the surface of the first electrically conductive layer to conduct the substrate bias voltage from the first electrically conductive layer to the backside surface of the die.
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Specification