Device and method for electrically or thermally coupling to the backsides of integrated circuit dice in chip-on-board applications

• US 6,339,256 B2
• Filed: 01/05/1999
• Issued: 01/15/2002
• Est. Priority Date: 06/06/1997
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Akram, Salman
• Primary Examiner(s): Wilczewski, Mary
• Assistant Examiner(s): GOODWIN, DAVID J
• Application Number:
  US09/225,278
• Publication Number:
  US 20010003373A1
• Time in Patent Office: 1,106 Days
• Field of Search: 257/723, 257/700, 257/758, 257/782, 257/686, 257/698, 257/703, 257/706, 257/712, 257/774, 361/780, 361/790, 361/794, 361/736, 361/761, 361/707, 361/711, 361/717, 361/718, 361/719
• US Class Current: 257/691
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85444 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/8547 Zirconium (Zr) as principal constituent
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10161 : with a rectangular active surface
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

An inventive printed circuit board for chip-on-board applications has a ground plane that is externally exposed through apertures in any overlying layers in the board so the backside surface of a bare integrated circuit die can be directly attached to the ground plane using a silver-filled epoxy. As a result, heat is conducted away from the die through the ground plane. Also, a substrate bias voltage can be supplied to the backside surface of the die through the ground plane to eliminate the need for an internal substrate bias to the die, and to eliminate the need for a substrate bias voltage bond pad on the front-side surface of the die.

Claims

1. A printed circuit board for chip-on-board applications, the printed circuit board comprising:

a first dielectric layer including a top surface;

a first conductive layer positioned adjacently above the top surface of the first dielectric layer and including an upwardly facing die-mounting surface within a chip-attach area of the first conductive layer for direct conductive attachment to a backside surface of a bare integrated circuit chip to establish at least one of electrical and thermal conduction between the top surface of the first conductive layer and a bare integrated circuit chip;

a second dielectric layer positioned adjacently above the upwardly facing die-mounting surface of the first conductive layer, the second dielectric layer having an aperture therein to further define the chip-attach area of the first conductive layer and to receive a bare integrated circuit chip;

a second conductive layer positioned adjacently below the first dielectric layer, the second conductive layer extending laterally underneath at least the chip-attach area of the first conductive layer, the second conductive layer vertically insulated from direct electrical communication with the first conductive layer;

an insulative substrate positioned adjacently below the second conductive layer; and

a layer of signal traces superimposed on the second dielectric layer in a substantially parallel relationship therewith, at least some of the signal traces of the layer of signal traces including bond pads for electrical connection to a front-side surface of a bare integrated circuit chip.

2. The printed circuit board of claim 1, wherein the layer of signal traces is positioned on a top surface of the second dielectric layer.

3. The printed circuit board of claim 1, wherein a portion of the aperture of the second dielectric layer extends generally about a periphery of the chip-attach area of the first conductive layer.

4. The printed circuit board of claim 1, wherein the signal traces are selected from a group comprising copper, gold, and platinum.

5. A multi-chip module comprising:

a first supporting substrate including an insulative surface;

a first conductive layer positioned adjacently above the insulative surface of the first supporting substrate and including a top surface with a plurality of localized die-attach areas thereon;

a plurality of bare integrated circuit dice, each associated with one of the plurality of die-attach areas, each of the plurality of bare integrated circuit dice including opposing front-side and backside surfaces, the front-side surface of each of the plurality of bare integrated circuit dice including a plurality of bond pads thereon;

a conductive die-attach material interposed between each of the bare integrated circuit dice and each associated localized die-attach area for directly attaching the backside surface of each die to its associated localized die-attach area to establish at least one of electrical and thermal conduction between each die and each of the localized die-attach areas of the top surface of the first conductive layer;

an insulating layer positioned adjacently above the top surface of the first conductive layer, the insulating layer having a plurality of apertures therein, each aperture in substantial registry with one of the attached bare integrated circuit dice;

a second conductive layer positioned adjacently below the first supporting substrate, the second conductive layer extending laterally underneath at least the plurality of localized die-attach areas of the first conductive layer, the second conductive layer vertically insulated from direct electrical communication with the first conductive layer by the first supporting substrate;

a second, insulative supporting substrate positioned adjacently below the second conductive layer;

a signal layer connected to the insulating layer in a substantially parallel relationship therewith, the signal layer having a plurality of conductor-devoid areas therein, each conductor-devoid area in substantial registry with one of the attached bare integrated circuit dice, the signal layer including a plurality of terminals; and

a plurality of conductors coupling the plurality of terminals of the signal layer to the plurality of bond pads on the front-side surfaces of the bare integrated circuit dice.

6. The multi-chip module of claim 5, wherein the signal layer comprises a plurality of signal traces.

7. The multi-chip module of claim 5, wherein the plurality of signal layer terminals comprises bond pads.

8. The multi-chip module of claim 5, wherein at least one of the bare integrated circuit dice comprises a dynamic random access memory die.

9. The multi-chip module of claim 5, wherein the conductive die-attach material comprises a conductive epoxy.

10. The multi-chip module of claim 9, wherein the conductive epoxy comprises a metal filled epoxy.

11. The multi-chip module of claim 10, wherein the metal filled epoxy comprises a silver filled epoxy.

12. The multi-chip module of claim 5, wherein the conductive die-attach material comprises a eutectic material.

13. The multi-chip module of claim 12, wherein the eutectic material comprises a gold and silver eutectic material.

14. The multi-chip module of claim 5, wherein the conductive die-attach material comprises a solder.

15. The multi-chip module of claim 5, wherein the conductive die-attach material comprises a conductive polyamide.

16. The multi-chip module of claim 5, wherein the conductive die-attach material comprises a thermally conductive die-attach material.

17. The multi-chip module of claim 5, wherein the plurality of conductors comprises wire bond conductors.

18. The multi-chip module of claim 5, wherein the plurality of conductors comprises TAB conductors.

19. An electronic device comprising:

a first supporting substrate including an insulative surface;

a first conductive layer positioned adjacently above the insulative surface of the first supporting substrate and including a top surface with a localized die-attach area thereon;

a bare integrated circuit die having opposing front-side and backside surfaces, the front-side surface having a plurality of bond pads thereon;

a conductive die-attach material for directly attaching the backside surface of the bare integrated circuit die to the localized die-attach area on the surface of the first conductive layer to establish at least one of electrical and thermal conduction between the backside surface of the bare integrated circuit die and the localized die attach area on the top surface of the first conductive layer;

an insulating layer positioned adjacently above the top surface of the first conductive layer, the insulating layer having an aperture therein in substantial registry with the attached bare integrated circuit die;

a second conductive layer positioned adjacently below the first supporting substrate, the second conductive layer extending laterally underneath at least the localized die-attach area of the first conductive layer, the second conductive layer vertically insulated from direct electrical communication with the first conductive layer;

a second supporting substrate positioned adjacently below the second conductive layer;

a signal layer connected to the insulating layer in a substantially parallel relationship therewith, the signal layer having an aperture therein in substantial registry with the attached bare integrated circuit die, the signal layer including a plurality of terminals; and

a plurality of conductors coupling the plurality of terminals of the signal layer to the plurality of bond pads on the front-side surface of the bare integrated circuit die.

20. The electronic device of claim 19, wherein the signal layer comprises a plurality of signal traces.

21. The electronic device of claim 19, wherein the plurality of signal layer terminals comprises bond pads.

22. The electronic device of claim 19, wherein the bare integrated circuit die comprises a dynamic random access memory die.

23. The electronic device of claim 19, wherein the conductive die-attach material comprises a conductive epoxy.

24. The electronic device of claim 23, wherein the conductive epoxy comprises a metal-filled epoxy.

25. The electronic device of claim 24, wherein the metal-filled epoxy comprises a silver-filled epoxy.

26. The electronic device of claim 19, wherein the conductive die-attach material comprises a thermally conductive die-attach material.

27. The electronic device of claim 19, wherein the plurality of conductors comprises wire bond conductors.

28. The electronic device of claim 19, wherein the plurality of conductors comprises tape-automated-bonding conductors.

29. A system for conducting heat away from a bare integrated circuit die, the system comprising:

a first dielectric layer;

a first thermally conductive layer positioned adjacently above the first dielectric layer, the first thermally conductive layer positioned internally in a printed circuit board, the first thermally conductive layer including a top surface with an externally accessible localized die-attach region;

a second dielectric layer having an aperture in substantial registry with the externally accessible localized die-attach region of the first thermally conductive layer, the second dielectric layer positioned adjacently above the first thermally conductive layer;

a second thermally conductive layer positioned adjacently below the first dielectric layer, the second thermally conductive layer extending laterally underneath at least the externally accessible localized die-attach region of the first thermally conductive layer, the second thermally conductive layer vertically insulated from direct electrical communication with the first thermally conductive layer; and

a thermally conductive die-attach material for directly attaching a backside surface of a bare integrated circuit die to the externally accessible localized die-attach region on the top surface of the first thermally conductive layer to establish thermal conduction between the bare integrated circuit die and the first thermally conductive layer.

30. The system of claim 29, wherein the first thermally conductive layer comprises a substantially continuous thermally conductive sheet.

31. The system of claim 29, wherein the first thermally conductive layer is also electrically conductive.

32. A system for supplying a substrate bias voltage to a bare integrated circuit die, the system comprising:

a substrate bias voltage generator for supplying a substrate bias voltage;

a first electrically conductive layer positioned within a printed circuit board and coupled to the substrate bias voltage generator, the first electrically conductive layer including a top surface with an externally accessible localized die-attach region;

a second electrically conductive layer positioned within a printed circuit board and coupled to the substrate bias voltage generator, the second electrically conductive layer positioned below and extending laterally underneath at least the externally accessible localized die-attach region of the first electrically conductive layer, the second electrically conductive layer vertically insulated from direct electrical communication with the first electrically conductive layer; and

an electrically conductive die-attach material for directly attaching a backside surface of a bare integrated circuit die to the externally accessible localized die-attach region on the top surface of the first electrically conductive layer to conduct the substrate bias voltage from the first electrically conductive layer to the backside surface of the bare integrated circuit die.

33. The system of claim 32, wherein the electrically conductive die-attach material comprises a conductive epoxy.

34. The system of claim 33, wherein the conductive epoxy comprises a metal-filled epoxy.

35. The system of claim 34, wherein the metal-filled epoxy comprises a silver-filled epoxy.

36. The system of claim 32, wherein the electrically conductive die-attach material comprises a eutectic material.

37. The system of claim 36, wherein the eutectic material comprises a gold and silver eutectic material.

38. The system of claim 32, wherein the electrically conductive die-attach material comprises a solder.

39. The system of claim 32, wherein the electrically conductive die-attach material comprises a conductive polyamide.

40. The system of claim 32, wherein the electrically conductive die-attach material is also a thermally conductive die-attach material.

41. The system of claim 32, wherein the first electrically conductive layer comprises a substantially continuous electrically conductive sheet.

42. A system for supplying a substrate bias voltage to a bare integrated circuit die, the system consisting essentially of:

a substrate bias voltage generator for supplying the substrate bias voltage;

a first electrically conductive layer positioned internally in a printed circuit board and coupled to the substrate bias voltage generator, the first electrically conductive layer including a top surface with an externally accessible localized die-attach region;

a second electrically conductive layer positioned within a printed circuit board and coupled to the substrate bias voltage generator, the second electrically conductive layer positioned below and extending laterally underneath at least the externally accessible localized die-attach region of the first conductive layer, the second conductive layer vertically insulated from direct electrical communication with the first electrically conductive layer; and

an electrically conductive die-attach material for directly attaching a backside surface of the bare integrated circuit die to the externally accessible localized die-attach region on the surface of the first electrically conductive layer to conduct the substrate bias voltage from the first electrically conductive layer to the backside surface of the die.