Measuring counter of the state of charge of the powering battery of an electronic appliance

• US 6,339,315 B1
• Filed: 02/14/2000
• Issued: 01/15/2002
• Est. Priority Date: 02/18/1999
• Status: Expired due to Term

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Pojer, Alex, Fraternali, Fabrizio, Mariani, Adalberto, Castelli, Claudia
• Primary Examiner(s): Wong, Peter S.
• Assistant Examiner(s): TIBBITS, PIA FLORENCE
• Application Number:
  US09/503,652
• Time in Patent Office: 701 Days
• Field of Search: 320/136, 320/106, 320/118, 324/428, 324/429, 324/430, 340/636
• US Class Current: 320/136
• CPC Class Codes: G01R 31/3648 comprising digital calculation means, e.g. for performing an algorithm
• CPC Class Codes: G01R 31/382 Arrangements for monitoring battery or accumulator variables, e.g. SoC

Abstract

A charge counter for monitoring the charge of the battery state of an electronic device includes a sensing circuit of the charge and discharge current of the battery. The sensing circuit includes a differential amplifier having inputs coupled to the terminals of a sensing resistor of the battery current, a resettable integrator of the output signal of the amplifier, a first comparator and a second comparator of the output signal of the integrator generating a logic charge interrupt signal and a logic discharge interrupt signal, respectively. The sensing circuit also includes a switch for discharging the capacitance of the integrator momentarily closed by a logic circuit at every transition of the output signal of one or the other of the first and second comparators. Further, the sensing circuit includes a processor for the interrupts which monitors the state of charge of the battery, a timer for measuring the time elapsing from the start of a new integration ramp and the switching instant of either one of the first and second comparators, and a nonvolatile memory register containing the measure of the time interval of integration of the offset of the differential amplifier up to the switching of either of the first and second comparators.

Claims

1. A charge counter for monitoring the charge and discharge current of a battery of an electronic device, the charge counter comprising:

a battery current sensing resistor;

a differential amplifier having inputs coupled to terminals of the battery current sensing resistor;

a resettable integrator of an output signal of the differential amplifier, and including a capacitor;

a first comparator of the output signal of the integrator for generating a logic charge interrupt signal;

a second comparator of the output signal of the integrator for generating a logic discharge interrupt signal;

a logic circuit for receiving the logic charge interrupt signal and the logic discharge interrupt signal;

a switch, which is momentarily closed by the logic circuit at every transition of the logic charge interrupt signal and the logic discharge interrupt signal, for discharging the capacitor of the integrator;

a processor for receiving the logic charge interrupt signal and the logic discharge interrupt signal to monitor the state of charge of the battery;

a timer measuring the time elapsing from the start of a new integration ramp and the switching instant of either one of the first and second comparators; and

a nonvolatile memory containing information corresponding to a time interval integration of an offset of the differential amplifier up to the switching instant of either one of the first and second comparators, the offset comprising a short-circuiting of the inputs of the differential amplifier during a trimming step and the information including a sign bit depending on which one of the first and second comparators was switched;

the processor incrementing or decrementing the computation of the logic charge interrupt signal and the logic discharge interrupt signal depending on the sign bit of the offset at an expiration of each time interval of integration of the offset stored in the memory.

2. A charge counter for monitoring the charge and discharge current of a battery of an electronic device, the charge counter comprising:

a battery current sensing resistor;

a differential amplifier connected to the battery current sensing resistor;

a resettable integrator for integrating an output signal of the differential amplifier, and including a capacitor;

a first comparator for comparing the output signal of the integrator with a first threshold to generate a logic charge interrupt signal;

a second comparator for comparing the output signal of the integrator with a second threshold to generate a logic discharge interrupt signal;

a logic circuit for receiving the logic charge interrupt signal and the logic discharge interrupt signal;

a switch connected to the capacitor of the integrator and controlled by the logic circuit to close at a transition of the logic charge interrupt signal and the logic discharge interrupt signal, for discharging the capacitor;

a timer measuring an elapsed time from a start of a new integration ramp and a switching instant of either one of the first and second comparators;

a nonvolatile memory for storing information regarding a time interval integration of an offset of the differential amplifier up to the switching instant of either one of the first and second comparators, the offset being a short-circuiting of the inputs of the differential amplifier during a trimming step and the information including a sign bit depending on which one of the first and second comparators switched; and

a processor for receiving the logic charge interrupt signal and the logic discharge interrupt signal to monitor the state of charge of the battery, and for incrementing or decrementing the computation of the logic charge interrupt signal and the logic discharge interrupt signal depending on the sign bit stored in the memory.

3. A charge counter according to claim 2, wherein the processor increments or decrements the computation of the logic charge interrupt signal and the logic discharge interrupt signal depending on the sign bit of the offset at an expiration of each time interval integration of the offset.

4. A charge counter according to claim 2, wherein the processor comprises an asynchronous counter.

5. An electronic device comprising:

a rechargeable battery;

a display for displaying information corresponding to a charge of the battery; and

a charge counter for monitoring the charge and discharge of the battery, the charge counter comprising

a battery current sensing resistor,

a differential amplifier connected to the battery current sensing resistor,

a resettable integrator for integrating an output signal of the differential amplifier, and including a capacitor,

a first comparator for comparing the output signal of the integrator with a first threshold to generate a logic charge interrupt signal,

a second comparator for comparing the output signal of the integrator with a second threshold to generate a logic discharge interrupt signal,

a logic circuit for receiving the logic charge interrupt signal and the logic discharge interrupt signal,

a switch connected to the capacitor of the integrator and controlled by the logic circuit to close at a transition of the logic charge interrupt signal and the logic discharge interrupt signal, for discharging the capacitor,

a timer measuring an elapsed time from a start of a new integration ramp and a switching instant of either one of the first and second comparators,

a nonvolatile memory for storing information regarding a time interval integration of an offset of the differential amplifier up to the switching instant of either one of the first and second comparators, the offset being a short-circuiting of the inputs of the differential amplifier during a trimming step and the information including a sign bit depending on which one of the first and second comparators switched, and

a processor for receiving the logic charge interrupt signal and the logic discharge interrupt signal to monitor the state of charge of the battery, and for incrementing or decrementing the computation of the logic charge interrupt signal and the logic discharge interrupt signal depending on the sign bit stored in the memory.

6. An electronic device according to claim 5, wherein the processor increments or decrements the computation of the logic charge interrupt signal and the logic discharge interrupt signal depending on the sign bit of the offset at an expiration of each time interval integration of the offset.

7. An electronic device according to claim 5, wherein the processor comprises an asynchronous counter.

8. A method for monitoring the charge and discharge current of a battery of an electronic device, the method comprising the steps of:

providing a battery current sensing resistor;

providing a differential amplifier connected to the battery current sensing resistor;

integrating an output signal of the differential amplifier with a resettable integrator including a capacitor;

comparing an integrated output signal with a first threshold to generate a logic charge interrupt signal;

comparing the integrated output signal with a second threshold to generate a logic discharge interrupt signal;

detecting a transition of the logic charge interrupt signal and the logic discharge interrupt signal;

discharging the capacitor at the transition of the logic charge interrupt signal and the logic discharge interrupt signal;

measuring an elapsed time from a start of a new integration ramp and a switching instant of either one of the first and second comparators;

storing information regarding a time interval integration of an offset of the differential amplifier up to the switching instant of either one of the first and second comparators, the offset being a short-circuiting of the inputs of the differential amplifier during a trimming step and the information including a sign bit depending on which one of the first and second comparators switched; and

incrementing or decrementing the logic charge interrupt signal and the logic discharge interrupt signal depending on the stored sign bit.

9. A method according to claim 8, wherein the logic charge interrupt signal and the logic discharge interrupt signal are incremented or decremented depending on the sign bit of the offset at an expiration of each time interval integration of the offset.

10. A method according to claim 8, wherein the logic charge interrupt signal and the logic discharge interrupt signal are incremented or decremented with an asynchronous counter.