Variable length coder of a video coder

• US 6,339,386 B1
• Filed: 10/15/1999
• Issued: 01/15/2002
• Est. Priority Date: 12/30/1998
• Status: Expired due to Term

• Current Assignee: LG-Ericsson Company Limited (Telefonaktiebolaget LM Ericsson)
• Original Assignee: LG Information & Communications Ltd. (LG Corporation)
• Inventors: Cho, Hyun Duk
• Primary Examiner(s): Young, Brian
• Assistant Examiner(s): NGUYEN, JOHN B
• Application Number:
  US09/418,573
• Time in Patent Office: 823 Days
• Field of Search: 341/67, 341/58, 341/59, 341/63, 341/100, 341/101, 341/60, 358/133
• US Class Current: 341/67
• CPC Class Codes: H03M 7/40 Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code
• CPC Class Codes: H04N 19/91 Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

Abstract

A variable length coder and encoding method of a video coder is disclosed. The present variable length coder includes a code buffer, a length buffer, and a bit packer of one register and one counter. Accordingly, the present invention allows a VLC with a compact size as well as lower power consumption.

Claims

1. A variable length coder (VLC), comprising:

a VLC code generator coupled to receive input symbols and generate code information and code length information;

a code buffer coupled to store the code information from the VLC code generator and output the code information at a constant rate;

a length buffer coupled to store the code length information from the VLC code generator and output the code length information at a constant rate; and

a bit packer coupled to receive the code information from the code buffer and the code length information from the length buffer, and to output code bits according to the code length information and provide a feedback signal to at least one of the code buffer and the length buffer.

2. The VLC of claim 1, wherein the bit packer comprises:

a parallel/serial register configured to read the code information upon receiving a read signal; and

a first counter configured to read the code length information upon receiving the read signal and counting for a duration of the code length, wherein the parallel/serial register outputs code bits of the code information while the first counter counts for the duration of the code length.

3. The VLC of claim 2, wherein the first counter comprises a down counter configured to count down from a value that is one less than the code length to ‘

0,’ and

outputs the read signal when the down counter reaches a value of ‘

0.’

4. The VLC of claim 2, wherein the first counter comprises an up counter and the up counter counts up from ‘

0’

to a value that is one less than the code length, and outputs the read signal when the up counter reaches the value which is one less than the code length.

5. The VLC of claim 2, wherein the bit packer further comprises:

a serial/parallel register coupled to receive the code bits from the parallel/serial register;

a second counter configured to count a duration of a prescribed code length; and

a channel buffer coupled to store code bits output from the serial/parallel register and outputting code bits at a constant rate, wherein the serial/parallel register concatenates the received code bits for the duration of the prescribed code length, and outputs the concatenated code bits to the channel buffer when the second counter attains a prescribed count value.

6. The VLC of claim 5, wherein the first counter is a down counter that counts down from a value that is one less than the code length to ‘

0,’ and

outputs the read signal when the down counter reaches a value of ‘

0.’

7. The VLC of claim 5, wherein the first counter is an up counter counts up from ‘

0’

to a value that is one less than the code length, and outputs the read signal when the up counter reaches the value which is one less than the code length.

8. The VLC of claim 5, wherein the second counter is a down counter that counts down from a value that is one less than the prescribed code length to ‘

0,’ and

wherein the serial/parallel register outputs the concatenated code bits when the down counter reaches a value of ‘

0.’

9. The VLC of claim 5, wherein the second counter is an up counter that counts up from ‘

0’

to a value which is one less than the prescribed code length, and wherein the serial/parallel register outputs the concatenated code bits when the down counter reaches the value which is one less than the predetermined code length.

10. The VLC of claim 5, wherein the serial/parallel register receives MSBs from the parallel/serial register.

11. The VLC of claim 1, wherein the feedback signal controls a reading of the code information by the bit packer.

12. The VLC of claim 1, wherein the bit packer reads code information in parallel and outputs code bits serially.

13. The VLC of claim 2, wherein the parallel/serial register outputs a single code bit at each count of the first counter.

14. A method of variable length coding input symbols, comprising:

(a) generating and outputting code information and code length information from input symbols;

(b) storing the code information in a code buffer and outputting the code information at a constant rate;

(c) storing the code length information in a length buffer and outputting the code length information at a constant rate; and

(d) receiving the code information from the code buffer and outputting the code information and a control signal based upon the code length information, wherein the control signal is provided to at least one of the code buffer and the length buffer.

15. The method of VLC of claim 14, wherein in step (d) further comprises:

(aa) reading the code information and reading the code length information upon receiving a read signal;

(bb) counting for a duration of the code length read; and

(cc) outputting code bits of the code information while counting for the duration of the code length.

16. The method of claim 15, wherein step (bb) comprises counting down from a value that is one less than the code length to ‘

0,’ and

outputting the read signal when a count reaches a value of ‘

0.’

17. The method of claim 15, wherein step (bb) comprises counting up from ‘

0’

to a value that is one less than the code length, and outputting the read signal when a count reaches the value that is one less than the code length.

18. The method of claim 15, wherein step (d) further comprises:

(dd) counting for the duration of a prescribed code length;

(ee) receiving and concatenating the code bits while counting for the duration of the prescribed code length;

(ff) outputting and storing the concatenated code bits to a buffer when the count attains a prescribed value; and

(gg) outputting the stored code bits at a constant rate.

19. The method of claim 18, wherein step (bb) comprises counting down from a value that is one less than the code length to ‘

0,’ and

outputting the read signal when a count reaches a value of ‘

0.’

20. The method of claim 18, wherein step (bb) comprises counting up from ‘

0’

to a value that is one less than the code length, and outputting the read signal when a count reaches the value that is one less than the code length.

21. The method of claim 18, wherein step (dd) comprises counting down from a value that is one less than the prescribed code length to ‘

0,’ and

wherein step (ff) comprises outputting the concatenated code bits when the count reaches a value of ‘

0.’

22. The method of claim 18, wherein step (dd) comprises counting up from ‘

0’

to a value that is one less that the prescribed code length, and wherein step (ff) comprises outputting the concatenated code bits when the count reaches the value that is one less than the predetermined code length.

23. The method of claim 14, wherein the control signal controls a reading of the code information.

24. The method of claim 14, wherein a bit packer receives the code information and generates the control signal.

25. A method of bit packing input code information of a variable length coder (VLC) in a wireless communication device, comprising:

reading the code information and code length information upon receiving a read signal;

counting for a duration of the code length read and generating the read signal at a prescribed count; and

outputting code bits of the code information while counting for the duration of the code length.

26. The method of claim 25, wherein the read signal controls the reading of the code information.

27. The method of claim 25, wherein a bit packer reads the code information from a code buffer and performs the counting, and wherein the read signal is fed back from the bit packer to the code buffer.