Display system having multiple memory elements per pixel

• US 6,339,417 B1
• Filed: 05/15/1998
• Issued: 01/15/2002
• Est. Priority Date: 05/15/1998
• Status: Expired due to Term

• Current Assignee: Compound Photonics Limited
• Original Assignee: Inviso, Inc.
• Inventors: Quanrud, William A.
• Primary Examiner(s): WU, XIAO MIN
• Application Number:
  US09/079,684
• Time in Patent Office: 1,341 Days
• Field of Search: 345/55, 345/87, 345/88, 345/89, 345/98, 345/100, 345/96, 345/81, 345/82, 345/83, 345/84, 345/102, 345/123, 345/157, 345/145, 345/206, 345/204, 345/205
• US Class Current: 345/98
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/0804 Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0857 Static memory circuit, e.g. flip-flop
• CPC Class Codes: G09G 2310/0235 Field-sequential colour display
• CPC Class Codes: G09G 3/2022 using sub-frames
• CPC Class Codes: G09G 3/2033 with splitting one or more sub-frames corresponding to the most significant bits into two or more sub-frames
• CPC Class Codes: G09G 3/32 semiconductive, e.g. using light-emitting diodes [LED]
• CPC Class Codes: G09G 3/34 by control of light from an independent source
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

A display matrix is provided for forming a composite image from a series of sub-images. The display matrix includes a plurality of display elements, each display element including a pixel, and a display circuit electrically connected to the pixel. Each display circuit includes a plurality of memory cells, and a selector for outputting to the pixel data from one memory cell at a time where the plurality of memory cells are non-addressably connected to the selector.

Claims

1. A display matrix comprising:

a plurality of display elements, each display element including

a pixel;

a display circuit electrically connected to the pixel, the display circuit including

a plurality of SRAM memory cells, and

a selector continuously electrically connected to more than one of the plurality of memory cells, the selector outputting to the pixel data from one memory cell at a time; and

peripheral control circuits electrically connected to the memory cells, the peripheral control circuits reading data from the memory cells, modifying the data, and writing the modified data to the memory cells.

2. The display matrix according to claim 1 wherein the memory cells include at least 3 memory cells.

3. The display matrix according to claim 1 wherein the memory cells include at least 9 memory cells.

4. The display matrix according to claim 1 wherein the reading, modifying and writing of data by the peripheral control circuits provides a cursor function to the display matrix.

5. The display matrix according to claim 1 wherein the reading, modifying and writing of data by the peripheral control circuits provides scroll function to the display matrix.

6. The display matrix according to claim 1 wherein the pixels form a liquid crystal display.

7. The display matrix according to claim 6 wherein the reading, modifying and writing of data by the peripheral control circuits provides an inversion function to the liquid crystal display matrix.

8. The display matrix according to claim 1 wherein peripheral control circuits include programmable registers that modify the read data.

9. The display matrix according to claim 1 wherein the display circuit includes one or more inputs for controlling the operation of the selector.

10. The display matrix according to claim 1 wherein the display circuit can be operated in a field sequential color (FSC) mode without having to write to the memory cells between displaying different fields.

11. The display matrix according to claim 1 wherein the display matrix does not have an external frame buffer.

12. The display matrix according to claim 11 wherein the display matrix can be operated in a field sequential color (FSC) mode without having to write to the memory cells between displaying different fields.

13. The display matrix according to claim 1 wherein the display matrix can be operated in a field sequential color (FSC) mode where a first set of memory cells defining a first bit plane are written to while a second set of memory cells defining a second bit plane are used to display a sub-image.

14. The display matrix according to claim 1 wherein an assignment of sub-images to different memory cells may be performed dynamically.

15. The display matrix according to claim 1 wherein the pixels of the plurality of display elements form a source object having an area equal to or less than about 400 mm².

16. The display matrix according to claim 1 wherein the pixels of the plurality of display elements form a source object having an area between about 20 mm² and 100 mm².

17. The display matrix according to claim 1 wherein the pixels have an area less than about 0.01 mm².

18. The display matrix according to claim 1 wherein the pixels have an area between about 50 μ

m² and 500 μ

m².

19. The display matrix according to claim 1 wherein the pixels are spatial light modulators.

20. The display matrix according to claim 1 wherein the pixels are light emitting elements.

21. The display matrix according to claim 1 wherein the display matrix is a component of a device selected from the group consisting of portable computers, personal communicators, personal digital assistants, modems, pagers, video and camera viewfinders, mobile phones, and television monitors.

22. A display matrix comprising:

a plurality of display elements, each display element including

a pixel;

a display circuit electrically connected to the pixel, the display circuit including

a plurality of SRAM memory cells, and

a selector permanently electrically connected to each of the plurality of memory cells, the selector outputting to the pixel data from one memory cell at a time; and

peripheral control circuits electrically connected to the memory cells, the peripheral control circuits reading data from the memory cells, modifying the data, and writing the modified data to the memory cells.

23. The display matrix according to claim 22 wherein the display matrix further includes a plurality of conductive elements, each conductive element electrically connecting a single member of the plurality of memory cells to the selector.

24. A display matrix comprising:

a substrate;

a plurality of pixels;

a plurality of display circuits, each display circuit positioned on a different region of the substrate, each display circuit electrically connected to a different pixel, each display circuit including

a plurality of SRAM memory cells, and

a selector connected to each of the plurality of memory cells, the selector outputting to the pixel data from one memory cell at a time; and

peripheral control circuits electrically connected to the memory cells, the peripheral control circuits reading data from the memory cells, modifying the data, and writing the modified data to the memory cells.

25. A display matrix comprising:

a plurality of display elements, each display element including

a pixel;

a display circuit electrically connected to the pixel, the display circuit including

a plurality of SRAM memory cells, and

a selector electrically connected to the plurality of memory cells for outputting to the pixel data from one memory cell at a time; and

peripheral control circuits electrically connected to the memory cells, the peripheral control circuits reading data from the memory cells, modifying the data, and writing the modified data to the memory cells;

wherein the memory cells are physically interdispersed among the selectors within the plurality of display elements.

26. A display system comprising:

a display matrix including a plurality of display elements, each display element including a pixel for forming a portion of a source object, a display circuit electrically connected to the pixel, the display circuit including a plurality of SRAM memory cells, and a selector continuously electrically connected to more than one of the plurality of memory cells, the selector outputting to the pixel date from one memory cell at a time;

peripheral control circuits electrically connected to the memory cells, the peripheral control circuits reading data from the memory cells, modifying the data, and writing the modified data to the memory cells;

a processor for controlling an operation of the peripheral control circuits.

27. The display system according to claim 26, further including a light emitting mechanism provided at each pixel.

28. The display system according to claim 26, further including a light modulating mechanism provided at each pixel.

29. The display system according to claim 28, further including an illumination source for illuminating the pixels.

30. The display system according to claim 28, wherein the said light modulating mechanism is a liquid crystal material.

31. The display system according to claim 26 wherein the reading, modifying and writing of data by the peripheral control circuits provides a cursor function to the display matrix.

32. The display system according to claim 26 wherein the display system is capable of composing a bit mapped image without the need of an external frame buffer.

33. The display system according to claim 26 wherein the reading, modifying and writing of data by the peripheral control circuits provides a scroll function to the display matrix.

34. The display system according to claim 26 wherein the pixels form a liquid crystal display and the reading, modifying and writing of data by the peripheral control circuits provides an inversion function to the liquid crystal display matrix.

35. The display system according to claim 26 wherein the display system further includes an illumination source capable of providing a plurality of different color illumination to the pixels, the particular color illumination provided to the pixels being coordinated by the peripheral control circuits with the read and write operations to the memory cells.

36. The display system according to claim 26, further including an illumination source which provides at least three different colors of illumination.

37. The display system according to claim 26 wherein the display system is a component of a device selected from the group consisting of portable computers, personal communicators, personal digital assistants, modems, pagers, video and camera viewfinders, mobile phones, and television monitors.

38. A virtual image display system comprising:

a display matrix including a plurality of display elements, each display element including a pixel for forming a portion of a source object, and a display circuit electrically connected to the pixel, the display circuit including a plurality of SRAM memory cells, and a selector continuously electrically connected to more than one of the plurality of memory cells, the selector outputting to the pixel data from one memory cell at a time;

peripheral control circuits electrically connected to the memory cells, the peripheral control circuits reading data from the memory cells, modifying the data, and writing the modified data to the memory cells; and

one or more magnification optics for magnifying images formed by the display matrix.

39. The virtual image display system according to claim 38 wherein the display system is a display component of a device selected from the group consisting of portable computers, personal communicators, personal digital assistants, modems, pagers, video and camera viewfinders, mobile phones, and television monitors.

40. A method for manipulating data initially stored in a display matrix which includes a plurality of display elements, each display element including a pixel, and a display circuit electrically connected to the pixel, the display circuit including a plurality of SRAM memory cells and a selector continuously electrically connected to more than one of the plurality of memory cells, the method comprising the steps of:

reading data from the memory cells to peripheral control circuits electrically connected to the memory cells;

modifying the data using the peripheral control circuits; and

writing the modified data to the memory cells.

41. The method according to claim 40 wherein reading, modifying and writing of data by the peripheral control circuits provides a cursor function to the display matrix.

42. The method according to claim 40 wherein reading, modifying and writing of data by the peripheral control circuits provides a scroll function to the display matrix.

43. The method according to claim 40 wherein the pixels form a liquid crystal display and reading, modifying and writing of data by the peripheral control circuits provides an inversion function to the liquid crystal display matrix.

44. The method according to claim 40 wherein reading, modifying and writing of data by the peripheral control circuits is performed without an external frame buffer.