Display control circuit and display control method

• US 6,339,422 B1
• Filed: 10/28/1998
• Issued: 01/15/2002
• Est. Priority Date: 10/28/1997
• Status: Expired due to Term

• Current Assignee: Sharp Corporation (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Kuwajima, Hidenori, Matsumoto, Toshio
• Primary Examiner(s): Hjerpe, Richard
• Assistant Examiner(s): DINH, DUC Q
• Application Number:
  US09/181,243
• Time in Patent Office: 1,175 Days
• Field of Search: 345/89, 345/87, 345/99, 345/100, 345/211, 345/213, 345/147, 345/204
• US Class Current: 345/204
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/2018 by time modulation using two or more time intervals
• CPC Class Codes: G09G 3/3622 using a passive matrix G09G3/3674 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3696 Generation of voltages supplied to electrode drivers
• CPC Class Codes: G09G 5/18 Timing circuits for raster scan displays specially adapted for television H04N ; synchronisation between the display unit and other display units, videodisc player G09G5/12
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

Abstract

A display control circuit of the present invention includes: a clock generator for generating a first clock signal having a single frequency; a frequency divider for dividing the frequency of the first clock signal generated by the clock generator, thereby providing a second clock signal; a selection signal generation section for generating a selection signal upon which one of a binary display mode and a gray-scale display mode is selected; a selector for selecting one of the first clock signal and the second clock signal based on the selection signal; and a display circuit for performing one of the binary display mode and the gray-scale display mode using the selected clock signal.

Claims

1. A display control circuit, comprising:

a clock generator for generating a first clock signal having a single frequency;

a frequency divider for dividing the frequency of the first clock signal generated by the clock generator, thereby providing a second clock signal;

a selection signal generation section for generating a selection signal upon which one of a binary display mode and a gray-scale display mode is selected;

a selector for selecting one of the first clock signal and the second clock signal based on the selection signal; and

a display circuit for performing one of the binary display mode and the gray-scale display mode using the selected clock signal.

2. A display control circuit according to claim 1, wherein the frequency divider further comprises a blocking section for blocking the frequency divider from receiving the first clock signal when the selector selects the first clock signal.

3. A display control circuit according to claim 1, further comprising a voltage adjustment section for adjusting a display device driving voltage based on the selection signal when the display circuit variably controls a timing of a control signal output to a display device.

4. A display control circuit, comprising:

a clock generator for generating a first clock signal having a single frequency;

a frequency multiplier for multiplying the frequency of the first clock signal generated by the clock generator, thereby providing a second clock signal;

a selection signal generation section for generating a selection signal upon which one of a binary display mode and a gray-scale display mode is selected;

a selector for selecting one of the first clock signal and the second clock signal based on the selection signal; and

a display circuit for performing one of the binary display mode and the gray-scale display mode using the selected clock signal.

5. A display control circuit according to claim 4, further comprising a voltage adjustment section for adjusting a display device driving voltage based on the selection signal when the display circuit variably controls a timing of a control signal output to a display device.

6. A display control method, comprising the steps of:

generating a selection signal upon which one of a binary display mode and a gray-scale display mode is selected;

selecting one of a first clock signal and a second clock signal obtained by dividing the frequency of the first clock signal based on the selection signal; and

performing one of the binary display mode and the gray-scale display mode using the selected clock signal.

7. A display control method according to claim 6, further comprising the step of generating one of a display setting voltage for the binary display mode and a display setting voltage for the gray-scale display mode based on the selection signal.

8. A display control method, comprising the steps of:

generating a selection signal upon which one of a binary display and a gray-scale display is selected;

selecting one of a first clock signal and a second clock signal obtained by multiplying the frequency of the first clock signal based on the selection signal; and

performing one of the binary display mode and the gray-scale display mode using the selected clock signal.

9. A display control method according to claim 8, further comprising the step of generating one of a display setting voltage for the binary display mode and a display setting voltage for the gray-scale display mode based on the selection signal.