Image scaling circuit for fixed pixed resolution display

• US 6,339,434 B1
• Filed: 11/23/1998
• Issued: 01/15/2002
• Est. Priority Date: 11/24/1997
• Status: Expired due to Term

• Current Assignee: Pixelworks Incorporated
• Original Assignee: Pixelworks Incorporated
• Inventors: Zimmerman, Alan L., West, Michael G., Greenberg, Robert Y.
• Primary Examiner(s): Brier, Jeffery
• Assistant Examiner(s): YANG, RYAN R
• Application Number:
  US09/198,314
• Time in Patent Office: 1,149 Days
• Field of Search: 382/298, 382/299, 345/127, 345/131, 345/132, 348/445
• US Class Current: 345/667
• CPC Class Codes: G06T 3/4023 based on decimating pixels or lines of pixels; based on inserting pixels or lines of pixels
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 5/391 Resolution modifying circuits, e.g. variable screen formats
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence

Abstract

An image scaling circuit for increasing or decreasing the size of a sampled image to match a fixed resolution display. The circuit includes means for resizing the image in the horizontal and vertical dimension using independent sample rate converters. The sample rate converters increase or decrease the image size by a factor of Lx/Mx in the horizontal dimension and Ly/My in the vertical dimension where Lx and Ly are integers and Mx and My are decimal numbers of arbitrary precision to provide fine scaling control. In addition, image warping is conveniently implemented by varying the down sample ratios Mx and My on a pixel by pixel and/or line by line basis.

Claims

1. A sample rate converter circuit for processing digital image data to resize a corresponding image, the sample rate converter circuit comprising:

input means for receiving an input stream of pixel values having a first sample rate;

an up sampler means for increasing the sample rate of the input stream to form an intermediate sample stream responsive to the input stream and having an up sample rate greater than the first sample rate;

FIR filter means for filtering the intermediate sample stream to form a FIR filtered intermediate sample stream; and

a down sampler means for decreasing the sample rate of the FIR filtered intermediate sample stream to form an output sample stream having a down sample rate less than the up sample rate wherein the down sampler means is arranged to reduce the sample rate of the intermediate sample stream by a down sampling factor, the down sampling factor being a selected decimal number of arbitrary precision.

2. A sample rate converter according to claim 1 wherein the up sampler means is arranged to increase the up sample rate by a selected integer factor.

3. A sample rate converter according to claim 2 wherein the integer factor is a power of two.

5. A sample rate converter according to claim 1 wherein the down sampler includes means for determining an output sample value responsive to values of an adjacent pair of samples of the FIR filtered intermediate sample stream.

6. A sample rate converter according to claim 5 including means for selecting one of an adjacent pair of samples of the FIR filtered intermediate sample stream and means for interpolating between the values of the selected adjacent pair of samples of the intermediate sample stream to form the output sample value.

7. A sample rate converter according to claim 1 including an image warping means for scaling the digital image data so as to produce an output image that is warped in relation to an input image.

8. A sample rate converter according to claim 7 wherein the image warping means includes means for varying the up sample rate or the down sample rate or both.

9. A sample rate converter according to claim 8 wherein the down sample rate is constant within each line and varies linearly from line to line of the output sample stream to create an output image having a keystone effect relative to the pixelated image.

10. A sample rate converter according to claim 8 wherein the down sample rate varies within each line of the output sample stream to create an output image having an aspect ratio different than an aspect ratio of the input image.

4. A sample rate converter circuit for processing digital image data to resize a corresponding image, the sample rate converter circuit comprising:

input means for receiving an input stream of pixel values having a first sample rate;

an up sampler means for increasing the sample rate of the input stream to form an intermediate sample stream responsive to the input stream and having an up sample rate greater than the first sample rate;

FIR filter means for filtering the intermediate sample stream to form a FIR filtered intermediate sample stream; and

a down sampler means for decreasing the sample rate of the FIR filtered intermediate sample stream to form an output sample stream having a down sample rate less than the up sample rate wherein the down sampler means is arranged to reduce the sample rate of the intermediate sample stream by a selected decimal factor;

wherein the down sampler means includes means for selecting the decimal factor by selecting one of an adjacent pair of samples of the FIR filtered intermediate sample stream as an output sample value.

11. A sample rate converter circuit for processing digital image data to modify the sample rate of a corresponding pixelated image, the sample rate converter circuit comprising:

an input buffer for receiving an input stream of pixel values having a first sample rate;

an up sampler circuit for increasing the sample rate of the input stream by an integer up sample factor L so as to form an intermediate sample stream responsive to the input stream and having an intermediate sample rate equal to L times the first sample rate;

a FIR filter for low-pass filtering the intermediate sample stream to form a FIR filtered sample stream; and

a down sampler circuit for decreasing the sample rate of the FIR filtered sample stream by a selected decimal down sample factor M so as to form an output sample stream having an output sample rate equal to 1/M times the intermediate sample stream sample rate whereby the output sample rate is equal to L/M times the first sample rate.

12. A sample rate converter circuit according to claim 11 wherein the up sample factor L is a power of two.

13. A sample rate converter circuit according to claim 11 wherein:

the FIR filter includes a plurality of multiplier circuits, each multiplier circuit arranged to multiply a selected input pixel value by a selected FIR coefficient to form a respective product; and

the FIR filter includes an adder arranged for summing the products together to calculate an output pixel value.

14. A sample rate converter circuit according to claim 13 wherein the plurality of multipliers are integer multipliers.

15. A sample rate converter circuit according to claim 13 wherein the input buffer comprises a pipeline formed of unit delay elements and wherein the input buffer comprises a plurality of taps, each tap connecting a respective one of the delay elements to an input of a corresponding one of the multiplier circuits for providing the selected input pixel value to the corresponding one of the multiplier circuits.

16. A sample rate converter circuit according to claim 13 wherein the input buffer comprises a pipeline of line memory buffers and wherein the input buffer comprises a plurality of taps, each tap connecting a respective one of the line memory buffers to an input of a corresponding one of the multiplier circuits for providing the selected input pixel value to the corresponding one of the multiplier circuits.

17. A sample rate converter circuit according to claim 13 wherein the FIR filter has a length equal to L*N, where L is the integer up sample factor and N is a selected integer.

18. A sample rate converter circuit for processing digital image data to modify the sample rate of a corresponding pixelated image, the sample rate converter circuit comprising:

an input buffer for receiving an input stream of pixel values having a first sample rate;

an up sampler circuit for increasing the sample rate of the input stream by an integer up sample factor L so as to form an intermediate sample stream responsive to the input stream and having an intermediate sample rate equal to L times the first sample rate;

a FIR filter for low-pass filtering the intermediate sample stream to form a FIR filtered sample stream; and

a down sampler circuit for decreasing the sample rate of the FIR filtered sample stream by a selected decimal down sample factor M so as to form an output sample stream having an output sample rate equal to 1/M times the intermediate sample stream sample rate whereby the output sample rate is equal to L/M times the first sample rate;

a memory for storing one or more sets of coefficients, each set of coefficients corresponding to a respective FIR phase; and

an FIR phase calculation circuit for determining a subset of input pixels and a corresponding FIR phase for each input pixel of the subset of input pixels;

wherein the FIR filter includes a plurality of multiplier circuits, each multiplier circuit arranged to multiply a selected input pixel value by a selected FIR coefficient to form a respective product; and

wherein the FIR filter includes an adder arranged for summing the products together to calculate an output pixel value.

19. A sample rate converter circuit according to claim 18 wherein each set of coefficients includes only coefficients corresponding to non-zero terms of the intermediate sample stream.

20. A sample rate converter circuit according to claim 18 wherein the FIR phase calculation circuit includes an image warping circuit for scaling the pixelated image by varying the up sample factor L or the down sample factor M or both.

21. A sample rate converter circuit according to claim 20 wherein the down sample factor M is constant within each line and varies linearly from line to line of the pixelated image to create an output pixel image having a keystone effect relative to the pixelated image.

22. A sample rate converter circuit according to claim 20 wherein the down sample factor M varies within each line of the pixelated image to create an output image having an aspect ratio different than an aspect ratio of the pixelated image.

23. A pixelated display controller integrated circuit, comprising:

a vertical scalar circuit; and

a horizontal scalar circuit, the vertical and horizontal scalar circuits together forming a two-dimensional image scaling subsystem;

wherein each of the vertical and horizontal scalar circuits comprises a multi-rate FIR filter system, each multi-rate FIR filter system comprising an up sampler circuit, a low-pass FIR filter, and a down-sampler circuit, wherein at least one of the up sampler circuits has an up sampling factor of L; and

wherein the down-sampler circuit corresponding to said one of the up sampler circuits has a down sampling factor of M, where M is a decimal number, whereby at least one of the vertical and horizontal scalar circuits provides a rational scaling factor equal to L/M.

24. A pixelated display controller system according to claim 23 wherein each low-pass FIR filter has a cutoff frequency approximately equal to the smaller of 1/M and 1/L.

25. A pixelated display controller system according to claim 23 wherein L=2ⁿ and n is a positive integer.

26. A pixelated display controller system according to claim 23 wherein M is represented as a 16-bit real number.

27. A pixelated display controller system according to claim 23 wherein the controller system is implemented in a monolithic integrated circuit.

28. A pixelated display controller system according to claim 23 wherein the vertical and horizontal scalar circuits implement scaling factors of Ly/My and Lx/Mx respectively, where Lx and Ly are powers of two and Mx and My are decimal numbers.

29. A sample rate converter according to claim 23 including an image warping means for scaling digital input image data so as to produce an output image that is warped in relation to an input image.

30. A sample rate converter according to claim 29 wherein the image warping means includes means for varying the up sample factor L or the down sample factor M or both.

31. A sample rate converter according to claim 30 wherein the down sample factor M is constant within each line and varies linearly from line to line of the output sample stream to create an output image having a keystone effect relative to the pixelated image.

32. A sample rate converter according to claim 30 wherein the down sample factor M varies within each line of the output sample stream to create an output image having an aspect ratio different than an aspect ratio of the input image.

33. A pixelated display controller system according to claim 23 including a frame buffer coupled to either the vertical or horizontal scaling circuits for storing pixelated images.

34. A pixelated display controller system according to claim 33 wherein the frame buffer converts an input refresh rate to an output refresh rate.

35. A pixelated display controller system according to claim 33 wherein the frame buffer includes synchronous dynamic random access memory.

36. A pixelated display controller system according to claim 35 wherein the frame buffer includes synchronous dynamic random access memory sufficient to store up to SXGA images at 24 bits per pixel or UXGA/HDTV images at 16 bits per pixel.

37. A method for rationally scaling a digital image having a series of digital image pixel values in a FIR filter scaling circuit, the method comprising:

receiving a series of input pixel values Ix;

selecting an up sample factor L, the up sample factor being a power of 2;

selecting a down sample factor M, the down sample factor M being a decimal number of arbitrary precision;

sizing the FIR filter scaling circuit as an integer multiple N times L so that the number of non-zero multiplies to realize the filter is N with every Lth filter coefficient multiplying a non-zero input pixel value;

selecting a group of non-zero input pixel values;

identifying a set of FIR filter coefficients for the group of non-zero input pixel values that multiply respective non-zero input pixel values in the FIR filter;

multiplying the group of input pixel values by the identified coefficients to form N products;

calculating a value of the initial output pixel position as a sum of the N products, whereby the number of multiply operations in the filter is reduced to N rather than N*L; and

repeating the selecting, identifying, multiplying, and calculating steps for subsequent output pixel positions so as to form a series of scaled output pixel values responsive to the series of input pixel values.

38. A method for rationally scaling a digital image having a series of digital image pixel values in a FIR filter scaling circuit, the method comprising:

receiving a series of input pixel values Ix;

selecting an up sample factor L, the up sample factor being a power of 2;

selecting a down sample factor M, the down sample factor M being a decimal number of arbitrary precision;

sizing the FIR filter scaling circuit as an integer multiple N times L so that the number of non-zero multiplies to realize the filter is N with every Lth filter coefficient multiplying a non-zero input pixel value;

selecting a group of non-zero input pixel values;

identifying a set of FIR filter coefficients for the group of non-zero input pixel values that multiply respective non-zero input pixel values in the FIR filter;

multiplying the group of input pixel values by the identified coefficients to form N products;

calculating a value of the initial output pixel position as a sum of the N products, whereby the number of multiply operations in the filter is reduced to N rather than N*L; and

repeating the selecting, identifying, multiplying, and calculating steps for subsequent output pixel positions so as to form a series of scaled output pixel values responsive to the series of input pixel values;

wherein identifying a set of FIR filter coefficients includes calculating a FIR phase and using the FIR phase to select one of a plurality of predetermined sets of coefficients.

39. A method for rationally scaling a digital image according to claim 38 wherein identifying a set of FIR filter coefficients includes storing the FIR coefficients in a memory and addressing the memory using the calculated FIR phase to access the selected set of coefficients.

40. A method for rationally scaling a digital image according to claim 38 wherein calculating the FIR phase includes:

defining a coefficient array as h(i) for i=0 to L*N−

1;

determining an integer output position by truncating a current output position plus 0.5;

determining an integer input pixel start position by truncating the integer output position plus L minus one divided by L; and

calculating the FIR phase as the input pixel start position*L minus the output position.

41. A method for rationally scaling a digital image according to claim 38 comprising normalizing each set of coefficients so that a sum of the coefficients for each set is equal to a predetermined constant whereby the FIR filter response to a constant input pixel value is a constant output.

42. A method for rationally scaling a digital image according to claim 38 including scaling the digital image to produce a scaled output image.

43. A method for rationally scaling a digital image according to claim 42 wherein scaling the digital image includes applying a keystone effect to the digital image by maintaining the down sample factor M constant within a line of the digital image and linearly varying the down sample factor M on a line by line basis.

44. A method for rationally scaling a digital image according to claim 42 wherein scaling the digital image includes converting an aspect ratio of the digital image to an aspect ratio of the output image, the aspect ratio of the digital image being different than the aspect ratio of the output image.

45. A method for rationally scaling a digital image according to claim 44 wherein converting the aspect ratio includes varying the down sample factor M of the digital image on a pixel by pixel basis.