Clock generating circuit having additional delay line outside digital DLL loop and semiconductor memory device including the same
First Claim
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1. A clock generating circuit generating an internal clock signal synchronized with an external clock signal, comprising:
- a first input buffer circuit generating a first internal signal according to voltage levels of said external clock signal and an inverted external clock signal;
a first delay circuit adding a delay control time to said first internal signal;
a phase difference control circuit setting said delay control time in accordance with phase difference between said first internal signal and an output signal of said first delay circuit;
a second input buffer circuit generating a second internal signal having phase inverted from that of said first internal signal, according to voltage levels of said external clock signal and said inverted external clock signal;
a second delay circuit adding said delay control time set commonly to said first delay circuit, to said second internal signal under control of said phase difference control circuit; and
a signal generating circuit generating said internal clock signal in response to output signals of said first and second delay circuits.
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Abstract
A DLL circuit includes two clock input buffers generating mutually complementary internal signals synchronized with an external clock signal a first delay circuit forming a delay loop arranged between one of the clock input buffers and a phase difference control circuit, a phase difference control circuit setting a delay control time so that a signal which has passed through the delay loop and one of the internal signals have matching phases, a second delay circuit applying the delay control time set commonly to the first delay circuit to the other one of the internal signal, and a pulse generating circuit generating an internal clock signal in response to output signals of the first and second delay circuits.
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Citations
20 Claims
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1. A clock generating circuit generating an internal clock signal synchronized with an external clock signal, comprising:
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a first input buffer circuit generating a first internal signal according to voltage levels of said external clock signal and an inverted external clock signal;
a first delay circuit adding a delay control time to said first internal signal;
a phase difference control circuit setting said delay control time in accordance with phase difference between said first internal signal and an output signal of said first delay circuit;
a second input buffer circuit generating a second internal signal having phase inverted from that of said first internal signal, according to voltage levels of said external clock signal and said inverted external clock signal;
a second delay circuit adding said delay control time set commonly to said first delay circuit, to said second internal signal under control of said phase difference control circuit; and
a signal generating circuit generating said internal clock signal in response to output signals of said first and second delay circuits. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
said phase difference control circuit generates a count data signal of M bits (M: - natural number) counted in accordance with said phase difference for setting said delay control time;
each of said first and second delay circuits includes a plurality of delay unit circuits connected in series, each adding a first delay time, and J (J;
natural number smaller than M) sub delay unit circuits provided for adding a second delay time shorter than said first delay time; and
delay time is added to said first and second internal signals by at least one of said delay unit circuits whose number corresponds to higher (M−
J) bits of said count data signal among said plurality of delay unit circuits and each of said J sub delay unit circuits selectively activated/inactivated in response to lower J bits of said count data signal.
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3. The clock generating circuit according to claim 2, wherein each of said first and second delay circuits further includes an internal node transmitting corresponding one of said first and second internal signals;
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first one of said sub delay unit circuits has a transfer gate turned on/off in response to the least significant bit of said count data signal and a capacitor having a capacitance value C, coupled in series between said internal node and a voltage node; and
Kth (K;
natural number not smaller than 2 and not larger than J) one of said sub delay unit circuits has a transfer gate turning on/off in response to the Kth bit from the least significant bit of said count data signal and a capacitor having a capacitance value 2(K−
1)·
C, coupled in series between said internal node and said voltage node.
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4. The clock generating circuit according to claim 2, wherein
each of said delay unit circuits includes a plurality of inverters connected in series, at least one of said plurality of inverters having a first MOS transistor and a first resistance element coupled in series between a first voltage and an output node of corresponding one of said inverters, and a second MOS transistor and a second resistance element coupled in series between a second voltage and said output node, said first and second MOS transistors having their gates electrically coupled to an input node of corresponding one of said inverters. -
5. The clock generating circuit according to claim 2, wherein
each of said first and second delay circuits further includes a timing control circuit designating transmission of the count data signal for a prescribed time period while corresponding one of said first and second internal signals is inactive, and a count data transmitting circuit taking and latching said count data signal in said prescribed time period designated by said timing control circuit; - and
said delay unit circuits and said sub delay unit circuits operate based on the count data signal latched by said count data transmitting circuit.
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6. The clock generating circuit according to claim 1, wherein
said first and second delay circuits each include a plurality of delay unit circuits connected in series with each other; -
said first and second internal signals pass through L, from the first to Lth (L;
natural number), of said plurality of delay unit circuits, in said first and second delay circuits respectively, in accordance with said delay control time; and
said plurality of delay unit circuits of said first delay circuit are arranged so that driving voltage of the first to Lth delay unit circuits is at the same level as driving voltage of the first to Lth delay unit circuits of said second delay circuit, respectively.
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7. The clock generating circuit according to claim 1, wherein
said signal generating circuit includes a first level converting circuit arranged outside a delay loop provided between said first input buffer circuit and said phase difference control circuit, and for converting amplitude of an output signal of said first delay circuit, a second level converting circuit for converting amplitude of an output signal of said second delay circuit, and a signal generation sub circuit generating said internal clock signal in response to output signals of said first and second level converting circuits. -
8. The clock generating circuit according to claim 1, further comprising:
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a voltage generating circuit receiving an external power supply voltage and generating an internal power supply voltage for driving said clock generating circuit;
a power supply line supplying said internal power supply voltage to said clock generating circuit; and
a stabilizing capacitance connected to said power supply line.
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9. A clock generating circuit generating an internal clock signal synchronized with an external clock signal, comprising:
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a first input buffer circuit generating a first internal signal in response to said external clock signal;
a first delay circuit adding a delay control time to said first internal signal;
a phase difference control circuit setting said delay control time in accordance with phase difference between said first internal signal and an output signal of said first delay circuit;
a second input buffer circuit generating a second internal signal having phase inverted from that of said first internal signal, in response to said external clock signal;
a second delay circuit adding said delay control time set commonly to said first delay circuit, to said second internal signal under control of said phase difference control circuit; and
a signal generating circuit generating said internal clock signal in response to output signals of said first and second delay circuits, wherein said first and second delay circuits each include a plurality of delay units circuits connected in series with each other;
said first and second internal signals pass through L, from the first to Lth (L;
natural number), of said plurality of delay unit circuits, in said first and second delay circuits respectively, in accordance with said delay control time; and
said plurality of delay unit circuits of said first delay circuits are arranged so that driving voltage of the first to Lth delay unit circuits is at the same level as driving voltage of the first Lth delay unit circuits of said second delay circuit, respectively;
said clock generating circuit further comprising;
first and second power supply lines for supplying the driving voltage from a voltage generating circuit to said first and second delay circuits respectively;
whereinsaid plurality of delay unit circuits in said first delay circuit are supplied with said driving voltage by said first power supply line;
said plurality of delay unit circuits in said second delay circuit are arranged parallel to said delay unit circuits of said first delay circuit respectively, and supplied with said driving voltage by said second power supply line; and
said plurality of delay unit circuits are arranged such that path length between said Lth delay unit circuit and said voltage generating circuit in said first delay circuit on said first power supply line is comparable to path length between said Lth delay unit circuit for the second delay circuit and said voltage generating circuit on said second power supply line. - View Dependent Claims (10)
said plurality of delay unit circuits are arranged such that path length on said first and second power supply lines between said voltage generating circuit and the Lth delay unit circuit is longer than that between said voltage generating circuit and (L− - 1)th delay unit circuit.
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11. A clock generating circuit generating an internal clock signal synchronized with an external clock signal, comprising:
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a first input buffer circuit generating a first internal signal in response to said external clock signal;
a first delay circuit adding a delay control time to said first internal signal;
a phase difference control circuit setting said delay control time in accordance with phase difference between said first internal signal and an output signal of said first delay circuit;
a second input buffer circuit generating a second internal signal having phase inverted from that of said first internal signal, in response to said external clock signal;
a second delay circuit adding said delay control time set commonly to said first delay circuit, to said second internal signal under control of said phase difference control circuit; and
a signal generating circuit generating said internal clock signal in response to output signals of said first and second delay circuits, wherein said first and second delay circuits each include a plurality of delay units circuits connected in series with each other;
said first and second internal signals pass through L, from the first to Lth (L;
natural number), of said plurality of delay unit circuits, in said first and second delay circuits respectively, in accordance with said delay control time; and
said plurality of delay unit circuits of said first delay circuits are arranged so that driving voltage of the first to Lth delay unit circuits is at the same level as driving voltage of the first Lth delay unit circuits of said second delay circuit, respectively;
said clock generating circuit further comprising a power supply line for generating the driving voltage from a voltage generating circuit to said first and second delay circuit;
whereinsaid Lth delay unit circuit of said first delay circuit and said Lth delay unit circuit of said second delay circuit are arranged adjacent to each other and supplied with said driving voltage from said power supply line. - View Dependent Claims (12)
said plurality of delay unit circuits are arranged such that path length on said power supply line between said voltage generating circuit and the Lth delay unit circuit is longer than that between said voltage generating circuit and (L− - 1)th delay unit circuit.
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13. A semiconductor memory device operating in synchronization with an external clock signal, comprising:
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a memory cell array having a plurality of memory cells;
a control circuit controlling a data access operation to said memory cells;
an output buffer circuit for outputting read data from said memory cell array; and
a clock generating circuit generating an internal clock signal synchronized with said external clock signal, serving as a trigger signal for a data output operation in said output buffer circuit, said clock generating circuit including an input buffer circuit generating an internal signal in response to said external clock signal, a delay circuit adding a delay control time to said internal signal, a signal generating circuit generating said internal clock signal in response to an output signal of said delay circuit, and a phase difference control circuit setting said delay control time in accordance with phase difference between said internal signal and an output signal of said delay circuit, said phase difference control circuit having a phase difference comparing circuit comparing the phase difference, a phase difference count circuit operating in response to an output of said phase difference comparing circuit and changing setting of said delay control time, and a count stopping circuit for stopping operation of said phase difference count circuit so as to fix the setting of said delay control time in a period when the read data is output from said semiconductor memory device in said data access operation. - View Dependent Claims (14)
said control circuit generates a count stopping signal activated in the period; said phase difference comparing circuit generates a count clock signal which is an operation clock of said phase difference count circuit; and
said count stopping circuit is provided between said phase difference comparing circuit and said phase difference count circuit and stops supply of said count clock signal to said phase difference count circuit when said count stopping signal is active.
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15. A semiconductor memory device operating in synchronization with an external clock signal, comprising:
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a memory cell array having a plurality of memory cells;
an output buffer circuit for outputting read data from said memory cell array; and
a clock generating circuit generating an internal clock signal synchronized with said external clock signal, serving as a trigger signal for a data output operation in said output buffer circuit, said clock generating circuit including an input buffer circuit generating an internal signal in response to said external clock signal, a delay circuit adding a delay control time to said internal signal, a delay replica circuit adding a dummy delay time corresponding to delay times generated in said output buffer circuit and said input buffer circuit to an output signal of said delay circuit, a program circuit for setting, in non-volatile manner, said dummy delay time by an external electrical input, a phase difference control circuit setting said delay control time in accordance with phase difference between said internal signal and an output signal from said delay replica circuit, and a signal generating circuit generating said internal clock signal in response to the output signal of said delay circuit. - View Dependent Claims (16, 17, 18, 19)
said program circuit generates a program signal of N bits (N: - natural number) set in non-volatile manner by the external electrical input;
said delay replica circuit includes even-numbered delay time control inverters connected in series between said delay circuit and said phase difference control circuit, each of said delay time control inverters having first and second MOS transistors having their gates coupled to an input node and drains coupled to an output node, N third MOS transistors coupled in parallel with each other between said first MOS transistor and a first voltage, turning on/off in response to N bits of said program signal, and N fourth MOS transistors coupled in parallel with each other between said second MOS transistor and a second voltage, turning on/off in response to N bits of said program signal.
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17. The semiconductor memory device according to claim 16, wherein the first ones of said third and fourth MOS transistors each have a channel width of W, and the Ith (I:
- natural number not smaller than 2 and not larger than N) ones of said third and fourth MOS transistors each have a channel width of 2(I−
1)·
W.
- natural number not smaller than 2 and not larger than N) ones of said third and fourth MOS transistors each have a channel width of 2(I−
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18. The semiconductor memory device according to claim 15, wherein
said delay replica circuit includes N (N: - natural number) replica unit circuits provided corresponding to respective bits of a program signal generated by said program circuit,
each of said replica unit circuits having a capacitor and a transfer gate turning on/off in response to the corresponding bit of said program signal, coupled in series between an internal node coupled between said delay circuit and said phase difference control circuit and a voltage node.
- natural number) replica unit circuits provided corresponding to respective bits of a program signal generated by said program circuit,
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19. The semiconductor memory device according to claim 18, wherein
said transfer gate in the first one of said replica unit circuits turns on/off in response to the first bit of said program signal and said capacitor in said first one has a capacitance value C, and said transfer gate in the Kth (K: - natural number not smaller than two and not larger than N) one of said replica unit circuits turns on/off in response to the Kth bit of said program signal and said capacitor in said Kth one has a capacitance value 2(K−
1)·
C.
- natural number not smaller than two and not larger than N) one of said replica unit circuits turns on/off in response to the Kth bit of said program signal and said capacitor in said Kth one has a capacitance value 2(K−
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20. A clock generating circuit generating an internal clock signal synchronized with an external clock signal comprising:
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an input buffer generating an internal signal in response to said external clock signal;
a delay circuit adding a delay control time to said internal signal and including a plurality of delay unit circuits connected in series, said delay unit circuits each including a plurality of inverters connected in series, at least one of said plurality of inverters having a first MOS transistor and a first resistance element coupled in series between a first voltage and an output node of the corresponding one of inverters, and a second MOS transistor and a second resistance element coupled in series between a second voltage and said output node, said first and second MOS transistors having their gates connected to an input node of the corresponding one of said inverters;
a phase difference control circuit setting said delay control time by setting the number of delay unit circuits to be activated in accordance with phase difference between said internal signal and an output signal of said delay circuit; and
a signal generating circuit generating said internal clock signal in response to the output signal of said delay circuit.
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Specification
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Current AssigneeRenesas Electronics Corporation
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Original AssigneeMitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
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InventorsKuge, Shigehiro
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Primary Examiner(s)Ho, Hoai V.
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Application NumberUS09/655,823Time in Patent Office496 DaysField of Search365/233, 365/194, 365/236, 365/189.01, 365/230.01, 327/291, 327/298, 327/277US Class Current365/194CPC Class CodesG11C 11/4082 Address Buffers; level conv...G11C 7/04 with means for avoiding dis...G11C 7/1066 Output synchronizationG11C 7/22 Read-write [R-W] timing or ...G11C 7/222 Clock generating, synchroni...G11C 7/225 Clock input buffersH03K 2005/00071 by adding capacitance as a ...H03K 5/131 Digitally controlledH03L 7/0814 the phase shifting device b...H03L 7/0816 the controlled phase shifte...H03L 7/089 the phase or frequency dete...
