Data transmission device

• US 6,339,622 B1
• Filed: 09/04/1998
• Issued: 01/15/2002
• Est. Priority Date: 10/29/1997
• Status: Expired due to Term

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: LG Semico Company Limited (SK Hynix Inc.)
• Inventors: Kim, Kuy Tae
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Fan, Chieh M.
• Application Number:
  US09/146,958
• Time in Patent Office: 1,229 Days
• Field of Search: 375/211, 375/259, 375/286, 375/287, 375/290, 326/59, 326/60
• US Class Current: 375/287
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: G09G 3/3685 Details of drivers for data electrodes
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/4925 using balanced bipolar ternary codes

Abstract

A data transmission device which improves data transmission efficiency is disclosed. A data transmission device includes a decoder converting a first binary data to a ternary data, a ternary data generator coupled to the decoder and generating three logic levels corresponding to a power source voltage, an intermediate voltage, and a ground voltage, the intermediate voltage having a voltage level between the power source voltage and the ground voltage, a ternary data detector coupled to the ternary data generator and converting the three logic levels from the ternary data generator to pairs of second binary data, and an encoder coupled to the data detector and restoring the pairs of second binary data to the first binary data.

Claims

1. A data transmission device, comprising:

a decoder converting a first binary data to a ternary data;

a ternary data generator coupled to the decoder and generating one pair of logic levels corresponding to the ternary data, a power source voltage, an intermediate voltage, and a ground voltage, the intermediate voltage having a voltage level between the power source voltage and the ground voltage;

a ternary data detector coupled to the ternary data generator and converting the one pair of logic levels from the ternary data generator to pairs of second binary data, wherein the ternary data detector comprises first and second inverters, each inverter comprising a PMOS and a NMOS, wherein a channel width/length ratio of the PMOS is different than a channel width/length ratio of the NMOS; and

an encoder coupled to the ternary data detector and restoring the pairs of second binary data to the first binary data.

2. The data transmission device according to claim 1, wherein the decoder comprises:

first, second, and third inverters respectively connected to first, second, and third input terminals of the decoder, and inverting input signals;

a level converting portion coupled to the first, second, and third inverters and converting levels of the input signals by selectively combining input signals from the input terminals with output signals from the inverters; and

a level output portion coupled to the level converting portion and outputting signals to the ternary data generator after selectively combining output signals from the level converting portion.

3. The data transmission device according to claim 2, wherein the level converting portion comprises a plurality of NAND gates for selectively combining input signals and inverse input signals to output signals to the level output portion.

4. The data transmission device according to claim 2, wherein the level output portion comprises a plurality of NAND gates and inverters for selectively combining output signals from the level converting portion.

5. The data transmission device as claimed in claim 1, wherein the ternary data generator comprises:

a PMOS having a source connected to the power source voltage and controlled by a gate input signal of the PMOS;

a first NMOS having a source connected to an half of the power source voltage and a drain commonly connected to a drain of the PMOS controlled by a gate input signal of the first NMOS; and

a second NMOS having a source connected to the ground voltage and a drain commonly connected to a drain of the PMOS and an output terminal controlled by a gate input signal of the second NMOS.

6. The data transmission device according to claim 5, wherein the ternary data generator has output signals of one pair of logic levels depending on each gate input signal from the decoder.

7. The data transmission device according to claim 1, wherein the encoder comprises:

an inverter portion inverting the pairs of the second binary data;

a data converting portion coupled to the inverter portion and selectively combining input signals from the ternary data detector and the inverter portion to output converted signals; and

a data output portion receiving the converted signals from the data converting portion and outputting signals.

8. The data transmission device according to claim 7, further comprising a state pin detecting a transmission state of the pairs of second binary date outputted from the ternary data detector.

9. The data transmission device according to claim 8, wherein the state pin determines whether the transmission state of the pairs of second binary data is in error when output signals from the ternary data detector are all “

0”

.

10. The data transmission device according to claim 1, wherein both the first and second inverters output high signals when input signals are 0 to 1 V.

11. The data transmission device according to claim 1, wherein one of the first and second inverters having a channel width/length ratio of the PMOS greater than the channel width/length ratio of the NMOS outputs a low signal when input signals are 2 to 3 V.

12. The data transmission device according to claim 1, wherein both the first and second inverters output low signals when input signals are 4 to 5 V.