Microcontroller system having allocation circuitry to selectively allocate and/or hide portions of a program memory address space

• US 6,339,815 B1
• Filed: 08/14/1998
• Issued: 01/15/2002
• Est. Priority Date: 08/14/1998
• Status: Expired due to Term

• Current Assignee: Greenliant LLC
• Original Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Phillips, Gary, Feng, Eugene
• Primary Examiner(s): Maung, Zarni
• Assistant Examiner(s): Chang, Jungwon
• Application Number:
  US09/134,242
• Time in Patent Office: 1,250 Days
• Field of Search: 713/200, 713/201, 713/300, 713/193, 713/2, 709/244, 711/154, 711/163, 711/115, 711/158, 711/170, 711/103, 711/101, 711/164, 711/152, 712/43, 365/218, 703/123, 235/380, 235/382.5, 235/492, 714/30
• US Class Current: 711/163
• CPC Class Codes: G06F 9/24 Loading of the microprogram
• CPC Class Codes: G06F 9/3802 Instruction prefetching

Abstract

A microcontroller system has a first and a second block of non-volatile programmable memory and includes a program memory space allocation circuitry. In a first mode of operation, the first and second blocks of programmable memory are prevented from being written by commands external to the microcontroller system. In a second mode, however, the first and second blocks of programmable memory are prevented from being written by commands external to the microcontroller system but the second block of programmable memory can be written based upon execution of commands stored in the first block of programmable memory. By having circuitry to so allocate the programmable memories, the security of the programmable memories is enhanced.

Claims

1. A unitary integrated memory circuit comprising:

a first block of nonvolatile programmable memory, having an addressable first memory space, and a second block of nonvolatile programmable memory, having an addressable second memory space;

a storage for storing a security code; and

memory space allocation circuit responsive to said security code, causing said integrated memory circuit to be operable in one of a plurality of the following modes;

first mode, wherein said first block of nonvolatile programmable memory and second block of nonvolatile programmable memory are prevented from being written by commands external to said integrated memory circuit;

second mode, wherein said first block of nonvolatile programmable memory and second block of nonvolatile programmable memory are prevented from being written by commands external to said integrated memory circuit, but said second block of nonvolatile programmable memory can be written based upon execution of commands stored in said first block of nonvolatile programmable memory.

2. The unitary integrated memory circuit of claim 1 wherein said storage is in said addressable first memory space.

3. The unitary integrated memory circuit of claim 1 wherein said first block of nonvolatile programmable memory and said second block of nonvolatile programmable memory are flash memories.

4. The unitary integrated memory circuit of claim 3 wherein in said first mode, said first block of nonvolatile programmable memory and said second block of nonvolatile programmable memory can be erased only by the erasure of the entire blocks of memory, and is otherwise not erasable by commands external to said integrated memory circuit.

5. The unitary integrated memory circuit of claim 1 further comprising:

a processor;

and wherein said unitary integrated memory circuit is operable in an internal mode wherein said processor retrieves program instructions stored in said first or second block of nonvolatile programmable memory and executes same.

6. The unitary integrated memory circuit of claim 5 wherein said memory space allocation circuit is further responsive to said security code in a third mode such that said processor is prohibited from retrieving program instructions from said first block of nonvolatile programmable memory;

and said processor may retrieve program instructions from said second block of nonvolatile programmable memory.

7. The unitary integrated memory circuit of claim 6 wherein said memory space allocation circuit is further responsive to said security code in a fourth mode such that said processor may retrieve program instructions from said first block of nonvolatile programmable memory;

and said processor may retrieve program instructions from said second block of nonvolatile programmable memory.

8. A unitary integrated memory circuit comprising:

a processor;

a first block of programmable memory, having an addressable first memory space, and a second block of programmable memory, having an addressable second memory space;

a storage for storing a security code; and

memory space allocation means responsive to said security code, causing said integrated memory circuit to be operable in one of a plurality of the following modes;

first mode, wherein said first block of programmable memory and second block of programmable memory are prevented from being written by commands external to said integrated memory circuit;

second mode, wherein said first block of programmable memory and second block of programmable memory are prevented from being written by commands external to said integrated memory circuit, but said second block of programmable memory can be written based upon execution of commands stored in said first block of programmable memory; and

third mode, wherein program instructions from said first block of programmable memory is prevented from being retrieved by said processor, and program instructions from said second block of programmable memory may be retrieved by said processor.

9. The unitary integrated memory circuit of claim 8 wherein said memory space allocation means is further responsive to said security code in a fourth mode such that said processor may retrieve program instructions from said first block of programmable memory;

and said processor may retrieve program instructions from said second block of programmable memory.

10. The unitary integrated memory circuit of claim 9 wherein said first and second blocks of programmable memory are flash memories.

11. The unitary integrated memory circuit of claim 10 wherein said storage is in said addressable first memory space.