Apparatus for establishing an electrical connection with a wafer to facilitate wafer-level burn-in and methods

• US 6,340,302 B1
• Filed: 02/06/2001
• Issued: 01/22/2002
• Est. Priority Date: 02/06/2001
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ladd, John W.
• Primary Examiner(s): Bradley, P. Austin
• Assistant Examiner(s): MCCAMEY, ANN M
• Application Number:
  US09/777,986
• Time in Patent Office: 350 Days
• Field of Search: 439/38-40, 324/760, 335/285
• US Class Current: 439/40
• CPC Class Codes: G01R 1/0416 Connectors, terminals G01R1/0425 and G01R1/0433 take precedence; with measurement function for battery poles G01R31/364
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2863 Contacting devices, e.g. sockets, burn-in boards or mounting fixtures in general G01R1/04
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: H01R 13/22 Contacts for co-operating by abutting
• CPC Class Codes: H01R 13/6205 Two-part coupling devices held in engagement by a magnet
• CPC Class Codes: H01R 2201/20 for testing or measuring purposes
• CPC Class Codes: Y10T 29/49004 including measuring or testing of device or component part
• CPC Class Codes: Y10T 29/49126 Assembling bases
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49169 Assembling electrical component directly to terminal or elongated conductor
• CPC Class Codes: Y10T 29/49174 Assembling terminal to elongated conductor
• CPC Class Codes: Y10T 29/49204 Contact or terminal manufacturing

Abstract

An electrical connector configured to nonrigidly apply force to a semiconductor substrate in directions substantially normal to a plane of the semiconductor substrate. The electrical connector includes a first member with an electrically conductive element and a first attractive element and a second member that includes a support element and a second attractive element. Attractive forces, such as magnetic attraction, between the first and second attractive elements secure the first and second members of the electrical connector to the semiconductor substrate in a manner that facilitates communication between the electrically conductive element of the first member and one or more semiconductor devices carried upon the semiconductor substrate. The electrical connector may be used in stress testing of semiconductor devices or to otherwise establish an electrical connection between one or more semiconductor devices, a ground, and a power source.

Claims

1. A method for establishing an electrical contact with a semiconductor device, comprising:

orienting a first member of an electrical connector in a first position on a semiconductor substrate so as to facilitate communication between a contact that communicates with the semiconductor device and said first member;

positioning a second member of said electrical connector at a second position on said semiconductor substrate, said second position being located opposite said first position; and

attracting said first and second members to one another such that said first and second members are nonrigidly biased against said semiconductor substrate in directions that are substantially normal to a plane of said semiconductor substrate.

2. The method of claim 1, wherein said attracting comprises magnetically attracting said first and second members to one another.

3. The method of claim 1, wherein said attracting comprises securing said first and second members to said semiconductor device.

4. A method for stress testing a semiconductor substrate including common ground and power contacts for a plurality of semiconductor devices carried upon the semiconductor substrate, the method comprising:

positioning a first member of an electrical connector adjacent each first position on an active surface of the semiconductor substrate so as to facilitate communication between said first member and at least one of the power contact and the ground contact;

positioning a second member of said electrical connector at a second position on a backside of the semiconductor substrate, said second position located opposite from said first position; and

securing said first and second members to the semiconductor substrate by way of mutually attractive forces between said first and second members.

5. The method of claim 4, wherein said securing comprises:

applying at least one magnetic field across the semiconductor substrate between said first and second positions.

6. The method of claim 4, wherein said securing comprises:

nonrigidly biasing said first and second members against the semiconductor substrate.

7. The method of claim 4, wherein said securing comprises:

biasing said first and second members against the semiconductor substrate in directions that are substantially normal to a plane of the semiconductor substrate.

8. The method of claim 4, further comprising:

positioning another first member of another electrical connector at another first position on said active surface so as to facilitate communication between said another first member and the other of the ground contact and the power contact;

positioning another second member of said another electrical connector at another second position on said backside, said another second position being located opposite from said another first position; and

securing said another first member and said another second member to the semiconductor substrate by mutually attractive forces between said another first member and said another second member.

9. The method of claim 8, further comprising:

applying a substantially constant amount of current to each semiconductor device of the plurality of semiconductor devices through said electrical connector and said another electrical connector.

10. The method of claim 9, further comprising:

heating the semiconductor substrate.

11. The method of claim 10, wherein said heating comprises cycling a temperature of the semiconductor substrate.

12. The method of claim 10, wherein said heating comprises varying a temperature of the semiconductor substrate.