Integrated low K dielectrics and etch stops

• US 6,340,435 B1
• Filed: 06/09/1999
• Issued: 01/22/2002
• Est. Priority Date: 02/11/1998
• Status: Expired due to Fees

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Yau, Wai-Fan, Huang, Judy H., Kim, Yunsang, Yin, Gerald, Yost, Dennis, Liu, Kuowei, Moghadam, Farhad K., Chapra, Nasreen Gazala, Shan, Hongquing, Bjorkman, Claes H., Cheung, David W., Tang, Betty, Yu, Min Melissa
• Primary Examiner(s): Gulakowski, Randy
• Assistant Examiner(s): KORNAKOV, MIKHAIL
• Application Number:
  US09/329,012
• Time in Patent Office: 958 Days
• Field of Search: 438/689, 438/702, 438/780, 216/13, 216/17, 216/18, 216/64, 216/72, 216/74, 216/76
• US Class Current: 216/72
• CPC Class Codes: C23C 16/401 containing silicon
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02208 the precursor containing a compound comprising Si
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/02304 formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/3121 Layers comprising organo-silicon compounds
• CPC Class Codes: H01L 21/31612 on a silicon body
• CPC Class Codes: H01L 21/31633 Deposition of carbon doped silicon oxide, e.g. SiOC
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence

Abstract

A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.

Claims

1. A process for depositing and etching intermetal dielectric layers, comprising:

depositing a first dielectric layer having a dielectric constant less than about 4.0;

depositing a second dielectric layer having a dielectric constant less than about 4.0 on the first dielectric layer; and

etching the second dielectric layer under conditions wherein the second dielectric layer has an etch rate that is at least about three times greater than an etch rate for the first dielectric layer.

2. The process of claim 1, wherein the first dielectric layer comprises silicon, oxygen, and at least about 5% carbon by atomic weight, and the second dielectric layer comprises silicon, oxygen, and less than about two-thirds of the carbon contained in the first dielectric layer.

3. The process of claim 2, wherein the first dielectric layer is etched to form vertical interconnects with a first gas mixture comprising one or more fluorocarbon compounds and one or more carbon:

oxygen compounds, and the second dielectric layer is etched to form horizontal interconnects with a second gas mixture comprising one or more fluorocarbon compounds and essentially no carbon;

oxygen compounds.

4. The process of claim 3, wherein the carbon:

oxygen compound is carbon monoxide.

5. The process of claim 1, wherein the first dielectric layer comprises silicon, oxygen, carbon, and at least 1% hydrogen by atomic weight, and the second dielectric layer comprises silicon, oxygen, carbon, and less than one-fifth of the hydrogen contained in the first dielectric layer.

6. The process of claim 5, wherein the first dielectric layer is etched to form vertical interconnects with a first gas mixture comprising one or more fluorocarbon compounds and one or more carbon:

oxygen compounds, and the second dielectric layer is etched to form horizontal interconnects with a second gas mixture comprising one or more fluorocarbon compounds and essentially no carbon;

oxygen compounds.

7. The process of claim 6, wherein the carbon:

oxygen compound is carbon monoxide.

8. The process of claim 1, wherein the first and second dielectric layers are deposited by oxidizing an organosilicon compound.

9. The process of claim 8, wherein the organosilicon compound is methylsilane or trimethylsiloxane.

10. The process of claim 1, wherein the first dielectric layer is deposited on a third dielectric layer having a dielectric constant less than about 4.0.

11. A process for depositing low dielectric constant layers, comprising:

varying one or more process conditions for depositing an organosilicon compound to obtain first and second dielectric layers having varying silicon, oxygen, carbon, and hydrogen contents and dielectric constants less than about 4; and

etching the second dielectric layer using conditions wherein the second dielectric layer has an etch rate that is at least 3 times greater than an etch rate for the first dielectric layer.

12. The process of claim 11, wherein the first dielectric layer contains at least 5% carbon by atomic weight or at least 1% hydrogen by atomic weight, and wherein the second dielectric layer contains less than two-thirds of the carbon in the first silicon oxide layer or less than one-fifth of the hydrogen in the first silicon oxide layer.

13. The process of claim 12 wherein the second dielectric layer is etched to form horizontal interconnects with a first gas mixture comprising one or more fluorocarbons and essentially no carbon:

oxygen compounds.

14. The process of claim 11, wherein the first dielectric layer is deposited on a third dielectric layer having silicon, oxygen, carbon, and hydrogen contents similar to the second dielectric layer.