Nonvolatile semiconductor memory device

• US 6,340,611 B1
• Filed: 07/28/2000
• Issued: 01/22/2002
• Est. Priority Date: 06/27/1997
• Status: Expired due to Term

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Narita, Kazuhito, Aritome, Seiichi, Watanabe, Toshiharu, Shimizu, Kazuhiro
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Smith, Bradley
• Application Number:
  US09/628,278
• Time in Patent Office: 543 Days
• Field of Search: 438/201, 438/199, 438/197, 438/200, 438/211, 438/257, 438/272
• US Class Current: 438/201
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A nonvolatile semiconductor memory device comprises a semiconductor substrate, element isolating regions provided in the semiconductor substrate, first element regions, each of which is defined by two adjacent ones of the element isolating regions, and memory cell transistors formed in the element regions, wherein each of the memory cell transistors comprises a first gate insulating film formed on a corresponding one of the element isolating regions, a floating gate electrode formed on the gate insulating film, a second gate insulating film formed on the floating gate electrode, and a control electrode formed on the second gate insulating film and connected in common to a specific number of ones of the memory cell transistors to serve as a word line, and the floating gate includes a first conductive member with side faces in contact with side ends of the two adjacent ones of the element isolating regions and a second conductive member electrically connected to the first conductive member and formed so as to bridge a gap between the two adjacent ones of element isolating regions.

Claims

1. A method for manufacturing a nonvolatile semiconductor memory device comprising the steps of:

forming a first conductive layer on a semiconductor substrate with a first insulating layer interposed therebetween;

forming a first mask layer having a predetermined first pattern on said first conductive layer;

forming a plurality of trenches in said substrate through said first conductive layer and said first insulating layer by etching with use of said first mask layer as a mask;

forming a second insulating layer in said plurality of trenches such that said insulating layer is formed up to an upper surface of said first mask layer;

exposing said first conductive layer by etching said first mask layer;

forming a second conductive layer on an upper surface of said first conductive layer and on an upper surface of said second insulating layer;

removing parts of said second conductive layer located on said second insulating layer to expose parts of said upper surface of said second insulating layer;

forming a third insulating film on said second conductive layer and said second insulating layer exposed; and

forming a third conductive layer on said third insulating layer.

2. The method according to claim 1, wherein said step of forming a second insulating layer in said plurality of trenches includes the steps of:

depositing said second insulating layer on an entire surface of said semiconductor substrate so as to fill said plurality of trenches with said second insulating layer; and

forming a plurality of isolation regions made of said second insulating layer by etching back said second insulating layer to expose an upper surface of said first mask layer.

3. The method according to claim 1, wherein said step of forming a second conductive layer on an upper surface of said first conductive layer and on an upper surface of said second insulating layer includes a step of forming said second conductive layer on an entire surface of said semiconductor substrate, after the step of exposing said first conductive layer.

4. The method according to claim 1, further comprising the steps of:

forming a second mask layer having a predetermined second pattern on said third conductive layer; and

etching said third conductive layer, said third insulating layer, said second conductive layer and said first conductive layer using said second mask layer as a mask.

5. The method according to claim 4, wherein said first mask layer has a plurality of stripe-form first openings substantially in parallel with each other, and said second mask layer has a plurality of stripe-form second openings intersecting said plurality of first openings.

6. The method according to claim 4, wherein said step of forming said plurality of trenches includes a step of forming said plurality of trenches into stripe forms each having a first width, respectively, said step of removing parts of said second conductive layer located on said second insulating layer includes a step of forming a plurality of stripe-form isolation regions each having a second width to remove said parts of said second conductive layer on said second insulating layer, respectively, and said second width is smaller than said first width.

7. The method according to claim 1, wherein said second insulating layer is made of silicon oxide and said first mask layer is made of silicon nitride.

8. A method for manufacturing a non-volatile semiconductor memory device comprising the steps of:

forming a first conductive layer on a semiconductor substrate with a first insulating layer interposed therebetween;

forming a first mask layer having a predetermined first pattern on said first conductive layer;

forming a plurality of trenches in said substrate through said first conductive layer and said first insulating layer by etching with use of said first mask layer as a mask;

forming a second insulating layer in said plurality of trenches;

forming a second conductive layer on an upper surface of said first conductive layer and on an upper surface of said second insulating layer;

removing parts of said second conductive layer located on said second insulating layer to expose parts of said upper surface of said second insulating layer;

forming a third insulating layer on said second conductive layer and said second insulating layer exposed; and

forming a third conductive layer on the third insulating layer.

forming a plurality of trenches in said substrate through said first conductive layer and said first insulating layer by etching with use of said first mask layer as a mask;

forming a second insulating layer in said plurality of trenches such that said insulating layer is formed up to an upper surface of said first conducting layer;

forming a second conductive layer on an upper surface of said first conductive layer and on an upper surface of said second insulating layer;

removing parts of said second conductive layer located on said second insulating layer to expose parts of said upper surface of said second insulating layer;

forming a third insulating layer on said second conductive layer and said second insulating layer exposed; and

forming a third conductive layer on said third insulating layer.

9. The method according to claim 8, wherein said step of forming a second insulating layer in said plurality of trenches includes the steps of:

depositing said second insulating layer on an entire surface of said semiconductor substrate so as to fill said plurality of trenches with said second insulating layer; and

forming a plurality of isolation regions made of said second insulating layer by etching back said second insulating layer to expose an upper surface of said first conductive layer.

10. The method according to claim 8, wherein said step of forming a second conductive layer on an upper surface of said first conductive layer and on an upper surface of said second insulating layer includes a step of forming said second conductive layer on an entire surface of said semiconductor substrate.

11. The method according to claim 8, further comprising the steps of:

forming a second mask layer having a predetermined second pattern on said third conductive layer; and

etching said third conductive layer, said third insulating layer, said second conductive layer and said first conductive layer using said second mask layer as a mask.

12. The method according to claim 11, wherein said first mask layer has a plurality of stripe-form first openings substantially in parallel with each other, and said second mask layer has a plurality of stripe-form second openings intersecting said plurality of first openings.

13. The method according to claim 11, wherein said step of forming said plurality of trenches includes a step of forming said plurality of trenches into stripe forms each having a first width, respectively, said step of removing parts of said second conductive layer includes a step of forming a plurality of stripe-form openings each having a second width on said plurality of stripe-form isolation regions to remove said parts of said second conductive layer, respectively, and said second width is smaller than said first width.

14. The method according to claim 8, wherein said second insulating layer is made of silicon oxide and said first mask layer is made of silicon nitride.

15. A method for manufacturing a nonvolatile semiconductor memory device comprising the steps of:

forming a first conductive layer on a semiconductor substrate with a first gate insulating layer interposed therebetween;

forming a first mask layer having a predetermined first pattern on said first conductive layer;

forming two trenches adjacent to and spaced apart with each oter in said substrate through said first conductive layer and said first gate insulating layer by etching with use of said first mask layer as a mask;

forming a first insulating layer in said two trenches;

forming a second conductive layer on an upper surface of said first conductive layer and said second insulating layer;

making said second conductive layer to terminate on said two isolation regions by etching such that said second said conductive layer bridges said two isolation regions, respectively;

forming a second gate insulating layer on said semiconductor substrate, after the steo of making said second conductive layer to terminate; and

forming a second conductive layer on said second gate insulating layer.

16. The method according to claim 15, wherein said step of forming a first insulating layer in said two trenches includes the steps of:

depositing said first insulating layer on an entire surface of said semiconductor substrate so as to fill said two trenches with said first insulating layer; and

forming to isolation regions made of said first insulating layer by etching back said first insulating layer to expose an upper surface of said first conductive layer.

17. The method according to claim 15, further comprising the steps of:

forming a second mask layer having a predetermined second pattern on said third conductive layer; and

etching said third conductive layer, said third insulating layer, said second conductive layer and said first conductive layer using said second mask layer as a mask.

18. The method according to claim 15, wherein said step of forming a first insulating layer in said two trenches includes a step of etching back said first insulating layer to an upper surface of said first mask layer, followed by etching said first mask layer without etching said first insulating layer.

19. The method according to claim 17, wherein said step of etching said third conductive layer, said third insulating layer, said second conductive layer and said first conductive layer using said second mask layer as a mask includes a step of exposing said second layer and said second gate insulating layer.

20. The method according to claim 18, after the step of exposing said second conductive layer, further comprising the steps of:

forming a second insulating layer on said semiconductor substrate;

selectively forming a contact hole in said second insulating layer to expose said second conductive layer; and

forming a via conductor by embedding a forth conductive layer into said contact hole.

21. The method according to claim 15, wherein said first insulating layer is made of silicon oxide and said first mask layer is made of silicon nitride.