Method and apparatus for phase interpolation

• US 6,340,909 B1
• Filed: 05/16/2000
• Issued: 01/22/2002
• Est. Priority Date: 01/30/1998
• Status: Expired due to Term

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Zerbe, Jared L., Tsang, Grace, Portmann, Clemenz L.
• Primary Examiner(s): Wells, Kenneth B.
• Application Number:
  US09/572,405
• Time in Patent Office: 616 Days
• Field of Search: 327/231, 327/237, 327/246, 327/256-258, 327/403, 327/404
• US Class Current: 327/246
• CPC Class Codes: H03K 5/13 Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
• CPC Class Codes: H03K 5/26 the characteristic being duration, interval, position, frequency, or sequence
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used

Abstract

A phase interpolater circuit includes a first adjustable current supply to generate a first current that is based on the amplitude of a first controlled voltage and a first current mirror circuit to generate a second current that is based on the first current. The phase interpolater circuit further includes a first current steering switch to steer the second current to one of first and second nodes to generate a first voltage transition at one of the first and second nodes, the second current being steered to the first node when a first input signal is in a first state and to the second node when the first input signal is in a second state.

Claims

1. A method of operation in a phase interpolator circuit, the method comprising:

generating a first current in relation to a control voltage using a current switch;

generating a second current in relation to the first current using a first current mirror circuit;

selectively steering the second current to a first selected node of first and second nodes to generate a first voltage transition at the first selected node, the second current being steered to the first node when a first input signal is in a first state and the second current being steered to the second node when the first input signal is in a second state;

generating a third current in relation to a second control voltage, wherein the second control voltage is complementary to the first control voltage;

generating a fourth current in relation to the third current using a second current mirror circuit; and

,

selectively steering the fourth current to a second selected node of the first and second nodes to generate a second voltage transition at the second selected node, the fourth current being steered to the first node when a second input signal is in the first state and the fourth current being steered to the second node when the second input signal is in the second state, wherein the second input signal is phase offset from the first input signal by a first phase angle.

2. The method of claim 1 further comprising:

sinking a portion of the second current from one of the first and second nodes in a first load circuit to generate a second voltage transition at the one of the first and second nodes.

3. The method of claim 1 further comprising:

amplifying voltages present at the first and second nodes to generate an output signal.

4. The method of claim 3 wherein the first phase angle is a quadrature phase angle.

5. The method of claims 1 further comprising:

sinking a portion of the first current to a ground potential terminal using a current source coupled to the first current mirror circuit.

6. The method of claim 1, further comprising:

removing an amount of current from the second current to produce a fifth current; and

detecting when the fifth current exceeds a threshold to generate a control signal.

7. The method of claim 6 further comprising:

selecting the first input signal from a plurality of input signals in response to the control signal.

8. The method of claim 7 wherein the plurality of input signals includes quadrature phase dock signals.

9. The method of claim 1 further comprising:

limiting a slew rate of a bias voltage in the first current mirror circuit using a capacitor coupled to the first current mirror circuit.

10. The method of claim 1 further comprising:

sensing common mode levels on the first and second nodes; and

reducing a difference between common mode levels of the first and second nodes to stabilize the common mode levels on the first and second nodes.

11. The method of claim 10 wherein the difference is reduced to a level that is set by a biased current source.

12. The method of claim 1 further comprising:

clamping common mode transients using a first diode element coupled between the first node and a capacitor electrode, and a second diode element coupled between the second node and the capacitor electrode, such that the transients are clamped using a charge stored on the capacitor electrode.

13. A phase interpolator circuit comprising:

a first current supply generating a first current in relation to a first control voltage;

a first current mirror circuit generating a second current related to the first current;

a first current steering switch steering the second current to a first selected node of first and second nodes to generate a first voltage transition at the first selected node, the second current being steered to the first node when a first input signal is in a first state and the second current being steered to the second node when the first input signal is in a second state;

a second current supply generating a third current in relation to a second control voltage;

a second current mirror circuit generating a fourth current related to the third current, wherein the fourth current is complementary to the second current; and

,

a second current steering switch steering the fourth current to a second selected node of the first and second nodes in response to a second input signal.

14. The phase interpolator of claim 13 further comprising:

a first load circuit sinking a portion of the second current from the first selected node.

15. The phase interpolator of claim 13 wherein a rising voltage transition is generated at one of the first and second nodes, and a falling voltage transition is generated at the other one of the first and second nodes.

16. The phase interpolator circuit of claim 13 further comprising:

an amplifier generating an output signal in response to voltage levels at the first and second nodes.

17. The phase interpolator of claim 16 wherein the second input signal has a first phase offset with respect to the first input signal.

18. The phase interpolator of claim 16 further comprising:

second load circuit sinking a portion of the fourth current from the second selected node.

19. The phase interpolator of claim 13 wherein the first current supply comprises first and second transistors having a common drain node and a common gate node, the first transistor being source coupled to a first bias source and the second transistor being source coupled to a second bias source.

20. The phase interpolator of claim 19 wherein the first transistor has a larger gate length than the second transistor.

21. The phase interpolator of claim 13 further comprising:

a capacitor coupled between a bias node of the first current mirror and a supply terminal.

22. The phase interpolator of claim 13 further comprising:

circuitry reducing the first current to produce a resultant current;

detector circuitry generating a control signal indicative of when the resultant current exceeds a threshold;

wherein the control signal is used to select the first input signal from a plurality of input signals.

23. The phase interpolator of claim 22 wherein the plurality of input signals comprises quadrature phase related signals.

24. The phase interpolator of claim 22 wherein the circuitry reducing the first current comprises a transistor coupling a supply terminal to the first current.

25. The phase interpolator of claim 13 further comprising:

first and second transistors having a common source node coupled to a current source, the first transistor having a gate coupled to the first node, and the second transistor having a gate coupled to the second node;

a second current mirror circuit to mirror an amount of current from the first node to a current at the drain of the second transistor; and

a third current mirror circuit to mirror an amount of current from the second node to a current at the drain of the first transistor.

26. The phase interpolator of claim 25 further comprising:

a first capacitor to limit a slew rate of a voltage at the drain of the first transistor; and

a second capacitor to limit a slew rate of a voltage at the drain of the second transistor.

27. The phase interpolator of claim 13 further comprising:

a first current source coupled to a first capacitor electrode;

a first diode element coupled between the first node and the first capacitor electrode; and

a second diode element coupled between the second node and the first capacitor electrode.

28. The phase interpolator of claim 27 further comprising:

a second current source coupled to a second capacitor electrode;

a third diode element coupled between the first node and the second capacitor electrode; and

a fourth diode element coupled between the second node and the second capacitor electrode.

29. The phase interpolator of claim 28 wherein:

the first capacitor electrode is included on a first capacitor, and another electrode of the first capacitor is coupled to a first supply node; and

the second capacitor electrode is included on a second capacitor, and another electrode of the second capacitor is coupled to a second supply node.

30. A phase interpolater comprising:

a first current supply generating a first current in relation to a first control voltage;

a first current mirror circuit generating a second current related to the first current;

a first current steering switch steering the second current to a first selected node of first and second nodes to generate a first voltage transition at the first selected node, the second current being steered to the first node when a first input signal is in a first state and the second current being steered to the second node when the first input signal is in a second state;

a second current supply generating a third current in relation to a second control voltage that is complementary to the first control voltage, the second current supply comprising;

first and second transistors having a common drain node and a common gate node, the first transistor being source coupled to a first bias source and the second transistor being source coupled to a second bias source, wherein the second transistor has a larger gate length than the first transistor.

31. A phase interpolator circuit comprising:

an adjustable current supply circuit generating differential currents in relation to differential control voltages;

a first current mirror circuit generating a first current related to the differential currents;

at least one current steering switch generating a voltage transition at one of first and second nodes in response to a first input signal, wherein the first current is steered to the first node when the first input signal is in a first state and the first current is steered to the second node when the first input signal is in a second state; and

a comparator circuit generating an output signal in relation to the first and second nodes.

32. The phase interpolator circuit of claim 31 further comprising:

a second current source generating a second current related to the differential currents; and

a first load circuit sinking a portion of the second current from one of the first and second nodes, wherein the sunk portion of the second current is sunk from the second node when the first input signal is in the first state, and the sunk portion of the second current is sunk from the first node when the first input signal is in the second state.

33. The phase interpolator circuit of claim 31 wherein the adjustable current supply circuit comprises:

a first differential amplifier including;

a current source;

a first transistor having a gate, a source and a drain, the gate receiving a first control voltage of the differential control voltages, and the source being coupled to the current source; and

a second transistor having a gate, a source and drain, the gate receiving a second control voltage of the differential control voltages, and the source being coupled to the current source; and

a second differential amplifier including;

a current source;

a first transistor having a gate, a source and a drain, the gate receiving the first control voltage, the source being coupled to the current source, and the drain being coupled to the drain of the first transistor of the first differential amplifier; and

a second transistor having a gate, a source and drain, the gate receiving the second control voltage, and the source being coupled to the current source, and the drain being coupled to the drain of the second transistor of the first differential amplifier.

34. The phase interpolator circuit of claim 33 wherein:

the first transistor of the first differential amplifier includes a gate length that is greater than a gate length of the second transistor of the first differential amplifier; and

the second transistor of the second differential amplifier includes a gate length that is greater than a gate length of the first transistor of the second differential amplifier.

35. The phase interpolator of claim circuit of claim 31 further comprising:

a capacitor having a first electrode coupled to a supply terminal;

a first current source coupled to a second electrode of the capacitor;

a first diode element coupled between the first node and the second electrode; and

a second diode element coupled between the second node and the second electrode.

36. The phase interpolator of claim 31 further comprising:

first and second transistors having a common source node coupled to a current source, the first transistor having a gate coupled to the first node, and the second transistor having a gate coupled to the second node;

a second current mirror circuit to mirror an amount of current from the first node to a current at a drain of the second transistor; and

a third current mirror to mirror an amount of current from the second node to a current at a drain of the second transistor.

37. A method of operation in a phase interpolator circuit, the method comprising:

generating a first current in relation to a control voltage using a current switch;

generating a second current in relation to the first current using a first current mirror circuit;

selectively steering the second current to a first selected node of first and second nodes to generate a first voltage transition at the first selected node, the second current being steered to the first node when a first input signal is in a first state and the second current being steered to the second node when the first input signal is in a second state;

reducing the second current to produce a third current;

generating a control signal when the third current reaches a threshold.

38. The method of claim 37 further comprising:

selecting the first input signal from a plurality of input signals in response to the control signal.

39. The method of claim 38 wherein the plurality of input signals includes quadrature phase clock signals.

40. A method of operation in a phase interpolator circuit, the method comprising:

generating a first current in relation to a control voltage using a current switch;

generating a second current in relation to the first current using a first current mirror circuit;

selectively steering the second current to a first selected node of first and second nodes to generate a first voltage transition at the first selected node, the second current being steered to the first node when a first input signal is in a first state and the second current being steered to the second node when the first input signal is in a second state;

detecting common mode levels on the first and second nodes; and

,

reducing any detected difference between common mode levels on the first and second nodes.

41. A phase interpolator circuit comprising:

a first current supply generating a first current in relation to a first control voltage;

a first current mirror circuit generating a second current related to the first current;

a first current steering switch steering the second current to a first selected node of first and second nodes to generate a first voltage transition at the first selected node, the second current being steered to the first node when a first input signal is in a first state and the second current being steered to the second node when the first input signal is in a second state;

circuitry reducing the first current to produce a resultant current;

detector circuitry generating a control signal indicative of when the resultant current exceeds a threshold;

wherein the control signal is used to select the first input signal from a plurality of input signals.

42. The phase interpolator of claim 41 wherein the plurality of input signals comprises quadrature phase related signals.