Low power buffer system for network communications

• US 6,341,135 B1
• Filed: 02/26/1998
• Issued: 01/22/2002
• Est. Priority Date: 02/26/1998
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: 3Com Corporation (HP Inc.)
• Inventors: Lo, Burton B., Pan, Anthony L., Fawal, Marwan A.
• Primary Examiner(s): TON, DANG T
• Application Number:
  US09/032,382
• Time in Patent Office: 1,426 Days
• Field of Search: 370/463, 370/214, 370/243, 370/244, 370/245, 370/247, 370/248, 370/249, 370/250, 370/251, 370/401, 370/419, 370/428, 370/347, 370/442, 370/441, 375/224, 375/212, 375/213, 375/215, 365/230.08, 365/230.02, 327/108, 327/109, 327/112, 333/177, 341/144
• US Class Current: 370/419
• CPC Class Codes: H04L 12/40032 Details regarding a bus interface enhancer
• CPC Class Codes: H04L 25/0266 Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/0286 Provision of wave shaping within the driver wave shaping per se H04L25/03834
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end

Abstract

NMOS transistor buffers are used to buffer the output of a system. The system can include a network interface card. The NMOS transistor buffers receive the output of the shaped Ethernet data signals and drive a transformer. The NMOS transistor buffers allow for low power consumption while a feedback monitoring system provides stability by controlling the inputs to the NMOS transistors.

Claims

1. A circuit for buffering a local area network communications signal prior to a transmission of said local area network communications signal, said circuit comprising:

an integrated circuit coupled to receive a twisted pair data transmission, including a first signal and a second signal;

a first transistor being formed in said integrated circuit, said first transistor coupled to generate a positive component of the local area network communications signal from the first signal, said first transistor being configured as a first amplifier for amplifying said first signal to generate said positive component; and

a second transistor being formed in said integrated circuit, said second transistor coupled to generate a negative component of the local area network communications signal from the second signal, said second transistor being configured as a second amplifier for amplifying said second signal to generate said negative component.

2. The circuit of claim 1 wherein said first transistor and said second transistor each include an NMOS transistor.

3. The circuit of claim 1 wherein the integrated circuit includes a first pin and a second pin, and wherein the gate of the first transistor is coupled to receive said first signal, wherein the drain of the first transistor is coupled to said first pin, and wherein the source of the first transistor is coupled to VSS.

4. The circuit of claim 1 further comprising a first operational amplifier and a second operational amplifier, said first operational amplifier and the second operational amplifier are configured to reduce the RC time constant of the first transistor and the second transistor.

5. The circuit of claim 1 wherein said integrated circuit is coupled to receive a feedback signal, said feedback signal is used for controlling said first signal and said second signal to ensure that said local area network signal conforms to Ethernet transmission requirements.

6. The circuit of claim 5 wherein said Ethernet transmission requirements include 10 MHz Ethernet transmission requirements.

7. The circuit of claim 5 wherein said Ethernet transmission requirements include 100 MHz Ethernet transmission requirements.

8. The circuit of claim 1 further comprising a filter circuit, said filter circuit not being formed on said integrated circuit, said filter circuit for filtering out high frequency components of said positive component and said negative component.

9. The circuit of claim 8 wherein said circuit is supported by a printed circuit board, wherein said filter circuit includes an isolation transformer, and wherein said isolation transformer is formed at least partially from traces on said printed circuit board.

10. A circuit for buffering a local area network communications signal prior to a transmission of said local area network communications signal, said local area network communications signal including a positive component and a negative component, said circuit comprising:

an integrated circuit;

a first transistor being formed in said integrated circuit, said first transistor coupled to generate said positive component from a first signal, said first transistor for amplifying said first signal to generate said positive component;

a second transistor being formed in said integrated circuit, said second transistor coupled to generate said negative component from a second signal, said second transistor for amplifying said second signal to generate said negative component;

a filter circuit, said filter circuit not being formed on said integrated circuit, said filter circuit for filtering out high frequency components of said positive component and said negative component; and

wherein said first transistor and said second transistor are configured as amplifiers, and said filter circuit includes a center tapped transformer, said center tapped transformer having a primary winding and a secondary winding, said primary winding having a center tap, a first terminal and a second terminal, and wherein said first terminal is coupled to receive said positive component from said first transistor, wherein said second terminal is coupled to receive said negative component from said second transistor, and wherein said center tap is coupled to one half of VDD.

11. A circuit for buffering Ethernet signals, said circuit comprising:

an integrated circuit for generating said Ethernet signals;

a transformer for isolating said integrated circuit and filtering said Ethernet signals, said transformer having a primary winding and a secondary winding, the primary winding including a first terminal and a second terminal; and

wherein said integrated circuit includes a first transistor and a second transistor, said first transistor and said second transistor each being configured as a common source amplifier, wherein said first transistor and said second transistor coupled to provide said Ethernet signals to said primary winding, the first terminal of the primary winding receiving a positive component a signal from the first transistor, and the second terminal of the primary winding is coupled to receive a negative component of the signal from the second transistor.

12. The circuit of claim 11 wherein said integrated circuit includes a first operational amplifier and a second operational amplifier, each operational amplifier being configured to reduce the RC time constant of said first transistor and said second transistor.

13. The circuit of claim 11 wherein said first transistor includes an NMOS transistor.