Apparatus and method for implementing a snoop bus protocol without snoop-in and snoop-out logic

• US 6,341,337 B1
• Filed: 01/30/1998
• Issued: 01/22/2002
• Est. Priority Date: 01/30/1998
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Pong, Fong
• Primary Examiner(s): Thai, Tuan V.
• Application Number:
  US09/016,208
• Time in Patent Office: 1,453 Days
• Field of Search: 711/3, 711/118, 711/119, 711/130, 711/133, 711/144, 711/145, 711/146, 711/148, 711/154, 711/167
• US Class Current: 711/146
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means

Abstract

The present invention is a method and apparatus that implements a snoop protocol in a multiprocessor system without the use of snoop-in and snoop-out logic units. The multiprocessor system includes a number of nodes connected by a bus operated in accordance with a snoop protocol and the MOSI cache coherency protocol. Each node includes a cache memory and a main memory unit including a shared memory region that is distributed in one or more of the cache memories of the nodes in the system. Each node includes a memory access unit having an export cache that stores identifiers associated with data blocks that have been modified by another node. Each data block in the main memory unit is associated with a state bit that indicates whether the data block is valid or invalid. The export cache and the state of each memory data block is used to determine whether a node should transmit a fetched data block to an initiator node in response to a read miss transaction. In this manner, the bus traffic is reduced since only the valid copy of the requested data item is transmitted to the initiator node.

Claims

1. A computer system comprising:

a snoop bus;

a plurality of nodes connected to the snoop bus, each node comprising;

a processor;

a main memory unit including a shared memory region associated with a respective node, the shared memory region including a multiplicity of shared memory datums that may be exported to one or more other nodes;

a cache memory including a portion of the shared memory associated with the node and a portion of the shared memory associated with another node;

a tag memory associated with the cache memory of the node, the tag memory storing one or more cache memory identifiers, each cache memory identifier identifying a cache memory datum stored in the cache memory of the node; and

a memory access unit associated with the main memory unit of the node, the memory access unit storing one or more main memory identifiers, each main memory identifier identifying a shared memory datum associated with the respective node that was exported to the cache memory of another node that modified the shared memory datum;

wherein when a read miss occurs an address is broadcasted on the snoop bus from an initiator node, the node associated with the broadcasted address fetches data stored in the associated main memory unit and transmits the fetched data to the initiator node when a main memory identifier associated with the broadcasted address is not found in the memory access unit.

2. The system of claim 1,

the main memory unit including one or more data blocks of shared memory, each data block associated with a state identifier, the state identifier indicating whether the corresponding data block is valid or invalid; and

wherein the case of a read miss, the node associated with the address transmits the fetched data to the initiator node when the state identifier of a data block corresponding to the address is valid.

3. The system of claim 1 wherein the cache memory is operated in accordance with a MOSI cache coherency protocol.

4. A method for accessing data in a computer system including a plurality of nodes connected to a snoop bus operated in accordance with a snoop bus protocol, each node including a processor, a cache memory, a main memory unit and a memory access unit, the method comprising the steps of:

associating with each main memory unit a shared memory region that is accessible by each node;

storing in the memory access unit a plurality of identifiers, each identifier representing a data block in the shared memory region associated with the node that has been exported to another node and that has been modified;

snooping a read miss transaction transmitted on the snoop bus from an initiator node, the read miss transaction including a request address;

searching the memory access unit for a main memory identifier including the request address;

when the request address is not found in the memory access unit;

fetching the corresponding data block from the associated main memory unit;

transmitting the data block to the initiator node; and

when the request address is found in the memory access unit, not transmitting the data block from the main memory unit to the initiator node.

5. The method of claim 4, further comprising the steps of:

storing in the memory access unit a main memory identifier for each data block in the main memory unit, each main memory identifier having a state indicating whether the data block is valid or invalid;

the transmitting step further comprising the steps of

searching the main memory identifiers to determine whether the state associated with the data block is valid; and

transmitting the data block to the initiator node when the state of the main memory identifier associated with the data block is valid.

6. The method of claim 4,

storing in each cache memory one or more data blocks from the shared memory region associated with one or more nodes;

associating with each data block in the cache memory a cache memory identifier, each cache memory identifier having a state indicating the status of the data block with respect to all nodes in the system;

searching for the request address in the cache memory;

when the request data is found in the cache memory, transmitting the corresponding data block from the cache memory to the initiator node when the corresponding state indicates the data has been modified by the processor associated with the respective node.

7. The method of claim 4, further comprising the steps of:

snooping a memory writeback transaction from the snoop bus;

receiving a modified data block;

writing the modified data block to the main memory unit;

marking the modified data block with a valid state.

8. The method of claim 4, further comprising the steps of:

snooping a write miss transaction from the snoop bus from a requesting node;

transmitting a copy of a data block corresponding to the write miss transaction to the requesting node from the main memory unit;

marking a main memory identifier associated with the exported data block with an invalid state; and

placing the main memory identifier associated with the exported data block in the memory access unit.