Apparatus and method for processor performance monitoring

• US 6,341,357 B1
• Filed: 10/08/1997
• Issued: 01/22/2002
• Est. Priority Date: 10/08/1997
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Ravichandran, Hari K.
• Primary Examiner(s): Trammell, James P.
• Assistant Examiner(s): Elisca, Pierre E.
• Application Number:
  US08/947,368
• Time in Patent Office: 1,567 Days
• Field of Search: 714/38, 714/25, 714/10, 714/31, 714/39, 714/718, 714/725, 395/704, 395/705, 716/5, 716/18, 717/4, 717/5, 717/11
• US Class Current: 714/38.1
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 11/348 Circuit details, i.e. tracer hardware

Abstract

The technology of the present invention pertains to an apparatus and method for implementing a hardware-based performance monitoring mechanism for use in analyzing the behavior of a program module. The apparatus includes probe logic hardware that monitors the program'"'"'s behavior in executing memory reference instructions. The probe logic hardware generates several probe signals which are transmitted to a performance monitor circuit when certain events occur. In an embodiment of the present invention, these events can be TLB or cache misses. The performance monitor circuit affixes a time stamp to the probe data and stores the time-stamped probe data in a temporary memory device until the data is stored in a magnetic storage device.

Claims

1. An apparatus for monitoring an execution behavior of a program, comprising:

a processor for executing a plurality of instructions;

a probe logic unit in communication with the processor that generates probe signals representative of memory access misses occurring in the processor;

a performance monitor circuit element that receives the probe signals and associates a temporal identifier signal with the probe signals; and

a memory for storing the temporal identifier signal and the probe signals, wherein the performance monitor circuit element stores the temporal identifier signal with the probe signals in the memory; and

a second high-speed memory and a program counter, the second high-speed memory generating a second high-speed memory miss signal,

wherein the probe logic unit generates a program counter signal, a second high-speed memory miss signal indicating a miss in the second high-speed memory a second high-speed memory miss count signal representing a number of misses in the second high-speed memory, and a time stamp signal when the second high-speed memory miss signal is active.

2. The apparatus of claim 1, further comprising:

one or more memory devices;

wherein the probe logic unit generates probe signals in response to a memory access miss signal when executing a specified instruction.

3. The apparatus of claim 1, further comprising:

a translation lookaside buffer (TLB);

wherein the probe logic unit generates probe signals recording a TLB miss when executing a specified instruction.

4. The apparatus of claim 1, wherein

the processor includes a translation lookaside buffer (TLB) and a program counter, the TLB generating a TLB miss signal;

and

the probe logic unit generates a program counter signal, a TLB identification signal indicating a miss in the TLB, a TLB miss count signal representing an accumulative count of TLB misses, and a time stamp signal when the TLB miss signal is activated.

5. The apparatus of claim 4, wherein

the probe logic unit includes a TLB miss counter coupled to the TLB miss signal, the TLB miss counter is incremented when the TLB miss signal is activated.

6. The apparatus of claim 1, wherein

the processor includes a first high-speed memory and a program counter, the first high-speed memory generating a first high-speed memory miss signal;

and

the probe logic unit generates a program counter signal, a first high-speed memory miss signal indicating a miss in the first high-speed memory, a first high-speed memory miss count signal representing a number of misses in the first high-speed memory, and a time stamp signal when the first high-speed memory miss signal is activated.

7. The apparatus of claim 6, wherein

the probe logic unit includes a first high-speed memory miss counter coupled to the first high-speed memory miss signal, the first high-speed memory miss counter is incremented when the first high-speed memory miss signal is activated.