Electronic component and method for manufacture

• US 6,342,411 B1
• Filed: 09/03/1999
• Issued: 01/29/2002
• Est. Priority Date: 09/03/1999
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Pitts, Bobby L. Jr.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): LOUIE, WAI SING
• Application Number:
  US09/389,638
• Time in Patent Office: 879 Days
• Field of Search: 251/15, 251/20, 251/22, 251/24, 251/27, 251/76, 251/190, 251/192, 251/194, 251/201, 251/284
• US Class Current: 438/173
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7785 with more than one donor layer

Abstract

A high voltage microwave field effect transistor (FET) and method for its manufacture. The FET (10) includes a channel layer (18) formed of compressively strained GaInP. Carrier confinement layers (16), (20) formed of tensile strained (AlGa)InP are formed both above (20) and below (16) the channel layer (20) to confine the carriers to the channel layer (20) and to provide a high breakdown voltage.

Claims

1. A method for manufacturing a field effect transistor comprising the steps of:

providing a substrate;

depositing a first layer of (AlGa)InP overlying the substrate;

depositing a second layer of compressive strained GaInP overlying the first layer and forming a first interface therewith, wherein said second layer is a channel layer;

depositing a third layer of tensile strained (AlGa)InP overlying the second layer and forming a second interface therewith; and

forming a remainder of the field effect transistor, wherein the field effect transistor has an increased breakdown voltage due to straining of the second and third layers.

2. The method of claim 1 further comprising the step of providing a delta doping layer in the first layer near the first interface during the deposition of the first layer.

3. The method of claim 1 further comprising the step of providing a delta doping layer in the third layer near the second interface during the deposition of the third layer.

4. The method of claim 1 further comprising the step of impurity doping the second layer during the deposition thereof.

5. The method of claim 1 wherein the steps of depositing a first layer and a third layer comprise depositing AlGa rich (AlGa)InP layers.

6. The method of claim 1 wherein the step of depositing a second layer comprises depositing an In rich GaInP layer.

7. The method of claim 1 further comprising the step of depositing a lattice matched fourth layer of GaInP overlying the third layer.

8. The method of claim 7 further comprising the step of depositing a layer of doped contact material overlying the fourth layer.

9. The method of claim 8 further comprising the step of forming source and drain contacts on the doped contact material.

10. The method of claim 7 further comprising the step of forming a gate electrode overlying the third layer.

11. A method for manufacturing a field effect transistor comprising the steps of:

providing a semi-insulating substrate;

depositing a first carrier confinement layer formed of a wide bandgap III-V material overlying the semi-insulating substrate;

depositing a compressive strained channel layer of the field effect transistor of wide bandgap III-V material overlying the first carrier confinement layer;

depositing a tensile strained second carrier confinement layer formed of a wide bandgap III-V material overlying the channel layer of the field effect transistor; and

forming a remainder of the field effect transistor.

12. The method of claim 11 wherein the field effect transistor has an increased breakdown voltage due to straining.

13. The method of claim 11 wherein the step of depositing a tensile strained second carrier confinement layer comprises depositing a layer of AlGa rich (AlGa)InP.

14. The method of claim 11 wherein the step of depositing a compressive strained channel layer comprises depositing a layer of In rich GaInP.