Nonvolatile semiconductor memory device

• US 6,342,715 B1
• Filed: 06/15/1998
• Issued: 01/29/2002
• Est. Priority Date: 06/27/1997
• Status: Expired due to Term

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Aritome, Seiichi, Watanabe, Toshiharu, Shimizu, Kazuhiro, Narita, Kazuhito
• Primary Examiner(s): CARROLL, JAMES J
• Application Number:
  US09/097,258
• Time in Patent Office: 1,324 Days
• Field of Search: 257/314, 257/315, 257/316, 257/321, 257/401, 257/510, 257/513, 438/258, 438/257
• US Class Current: 257/314
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A nonvolatile semiconductor memory device comprises a semiconductor substrate, element isolating regions provided in the semiconductor substrate, first element regions, each of which is defined by two adjacent ones of the element isolating regions, and memory cell transistors formed in the element regions, wherein each of the memory cell transistors comprises a first gate insulating film formed on a corresponding one of the element isolating regions, a floating gate electrode formed on the gate insulating film, a second gate insulating film formed on the floating gate electrode, and a control electrode formed on the second gate insulating film and connected in common to a specific number of ones of the memory cell transistors to serve as a word line, and the floating gate includes a first conductive member with side faces in contact with side ends of the two adjacent ones of the element isolating regions and a second conductive member electrically connected to the first conductive member and formed so as to bridge a gap between the two adjacent ones of element isolating regions.

Claims

1. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate;

a plurality of trenches provided in said semiconductor substrate, each of said plurality of trenches having an insulator embedded therein, side surfaces of said embedded insulator being substantially perpendicular to said semiconductor substrate;

a plurality of element regions, each being sandwiched between two adjacent embedded insulators; and

a plurality of memory cell transistors and a plurality of select transistors formed in said plurality of element regions, wherein

each of said plurality of memory cell transistors includes

a first gate insulating film formed on a corresponding one of said plurality of first element regions,

a charge storage layer formed on said first gate insulating film, side surfaces of said charge storage layer contacting two embedded insulators located on opposite sides of said charge storage layer,

a second gate insulating film formed on said charge storage layer, and

a control gate electrode formed on said second gate insulating film, and

each of said plurality of select transistors includes

a third gate insulating film formed on a corresponding one of said plurality of element regions,

a gate layer formed on said third gate insulating film, side surfaces of said gate layer contacting two embedded insulators located on opposite sides of said gate layer, and

a select gate electrode formed on said gate layer and electrically connected to said gate layer.

2. The nonvolatile semiconductor memory device according to claim 1, wherein each of said control gate electrode and said select gate electrode includes a first conductive layer that contacts said second gate insulating film and a second conductive layer that contacts said first conductive layer, said first conductive layer of said select gate electrode being formed on the same layer as that of said second gate insulating film above said embedded insulators, and said second conductive layer of said select gate electrode being connected to said gate layer above said embedded insulators.

3. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate;

a plurality of trenches provided in said semiconductor substrate, each of said plurality of trenches having an insulator embedded therein, side surfaces of said embedded insulator therein being substantially perpendicular to said semiconductor substrate;

a plurality of first element regions, each of which is defined by two adjacent embedded insulators; and

a plurality of memory cell transistors formed in said plurality of first element regions, respectively,

each of said plurality of memory cell transistors comprising;

a first gate insulating film formed on a corresponding one of said plurality of first element regions,

a charge storage layer formed on said first gate insulating film,

a second gate insulating film formed on said charge storage layer, and

a control gate electrode formed on said second gate insulating film and connected in common to a predetermined number of said plurality of memory cell transistors to serve as a word line, wherein

said charge storage layer includes a first conductive layer, side surfaces of which contact side surfaces of two embedded insulators located on opposite sides of said charge storage layer, and a second conductive layer electrically connected to said first conductive layer and extending over upper surfaces of said embedded insulators which are adjacent to said first conductive layer.

4. The nonvolatile semiconductor memory device according to claim 3, wherein a position of a top surface of said first conductive layer is substantially aligned with the upper surfaces of said two embedded insulators.

5. The nonvolatile semiconductor memory device according to claim 3, wherein a position of a top surface of said first conductive layer is lower than a position of said upper surfaces of said two embedded insulators located on opposite sides of said charge storage layer, and

said second conductive layer has a portion that contacts side surfaces of said two embedded insulators located on opposite sides of said charge storage layer and said upper surfaces of said two embedded insulators.

6. The nonvolatile semiconductor memory device according to claim 3, further comprising a plurality of select transistors which are formed in said plurality of first element regions and select a predetermined memory cell transistor, wherein each of said select transistors includes;

a third gate insulating film formed on a corresponding one of said plurality of first element regions,

a first gate layer formed on said third gate insulating film, side surfaces of which contact said two embedded insulators, and

a select gate electrode electrically connected to said first gate layer and made of the same layer as that of said control gate electrode.

7. The nonvolatile semiconductor memory device according to claim 6, wherein said first gate layer includes

a third conductive layer made of the same layer as that of the first conductive layer of each of said plurality of memory cell transistors, and

a fourth conductive layer electrically connected to said third conductive layer and made of the same layer as that of said second conductive layer of each of said plurality of memory cell transistors.

8. The nonvolatile semiconductor memory device according to claim 6, wherein the same layer as that of said second gate insulating film is formed on said embedded insulator that isolate said plurality of select transistors from each other.

9. The nonvolatile semiconductor memory device according to claim 8, wherein each of said control gate electrode and said select gate electrode includes a first conductive layer that contacts said second gate insulating film and a second conductive layer that contacts said first conductive layer, said first conductive layer of said select gate electrode being formed on said same layer of said second gate insulating film above a corresponding one of said embedded insulators, and said second conductive layer of said select gate electrode being connected to said first gate layer above a corresponding one of said plurality of first element regions.

10. The nonvolatile semiconductor memory device according to claim 3, further comprising:

a second element region formed apart from said plurality of first element regions, and

a peripheral circuit transistor formed in said second element region to drive said plurality of memory cell transistors, said peripheral circuit transistor including a fourth gate insulating film formed on said second element region and a gate electrode formed on said fourth gate insulating film, wherein

said gate electrode of said peripheral circuit transistor includes

a fifth conductive layer made of the same layer as that of said first conductive layer of each of said plurality of memory cell transistors, and

a sixth conductive layer electrically connected to said fifth conductive layer and made of the same layer as that of said second conductive layer of each of said plurality of memory cell transistors.

11. The nonvolatile semiconductor memory device according to claim 3, wherein a difference in height between a surface of said first conductive layer of said charge storage layer electrode and said upper surfaces of said embedded insulators is substantially the same throughout said plurality of memory cell transistors.

12. The nonvolatile semiconductor memory device according to claim 11, wherein a thickness of said first conductive layer varies among said plurality of memory cell transistors.

13. The nonvolatile semiconductor memory device according to claim 3, wherein opposite side faces of said second conductive layer on said two adjacent embedded insulators are tapered.

14. The nonvolatile semiconductor memory device according to claim 13, wherein the entire opposite side faces of said second conductive layer and said two adjacent ones of said plurality of embedded insulators are tapered.

15. The nonvolatile semiconductor memory device according to claim 3, wherein each of said plurality of first element regions is formed in a line-form and plural of said plurality of memory cell transistors are formed in one of said plurality of first element regions, each of said plurality of memory cell transistors having a source and a drain region formed so as to sandwich said charge storage layer electrode in one of said plurality of first element regions and sharing one of said source and said drain region with adjacent one of said plurality of memory cell transistors.

16. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate;

a plurality of trenches provided in said semiconductor substrate;

a plurality of element regions, each being sandwiched between two adjacent embedded insulators; and

a plurality of memory cell transistors and a plurality of select transistors formed in said plurality of element regions, wherein

each of said plurality of memory cell transistors includes

a first gate insulating film formed on a corresponding one of said plurality of element regions,

a charge storage layer which is formed on said first gate insulating film and side surfaces of which contact two embedded insulators located on opposite sides of said charge storage layer,

a second gate insulating film formed on said charge storage layer, and

a control gate electrode which is formed on said second gate insulating film and extends over said two embedded insulators located on opposite sides of said charge storage layer, and

each of said plurality of select transistors includes

a third gate insulating film formed on a corresponding one of said plurality of element regions,

a gate layer which is formed on said third gate insulating film and side surfaces of which contact two adjacent embedded insulators, and

a select gate electrode which is formed on said gate layer and electrically connected to said gate layer and extends over said two adjacent embedded insulators, wherein

a thickness of a corresponding one of said embedded insulators under said select gate electrode is greater than a thickness of said corresponding one of said embedded insulators under said control gate electrode.

17. The nonvolatile semiconductor memory device according to claim 16, further comprising a first region that is formed in each of said plurality of element regions and functions as one of a source and a drain region of each of said plurality of select transistors, a second region that is formed in each of said plurality of element regions and functions as one of a source and a drain region of each of said plurality of memory cell transistors, and a third region that is formed in each of said plurality of element regions and functions as the other of said source and said drain region for one of said plurality of select transistors and one of said plurality of memory cell transistors adjacent to said one of said plurality of select transistors and is shared by said one of said plurality of select transistors and said one of said plurality of memory cell transistors, wherein

a distance from a top surface of said gate layer of each of said plurality of select transistors to a top surface of a portion isolating said first region in said embedded insulators is equal to or less than a distance from a top surface of said charge storage layer electrode at each of said plurality of memory cell transistors to a top surface of a portion isolating said second region in said embedded insulators.

18. The nonvolatile semiconductor memory device according to claim 17, wherein a film thickness of a portion isolating said first region in said embedded insulators is equal to or larger than a film thickness of a portion isolating said second region in said embedded insulators.

19. The nonvolatile semiconductor memory device according to claim 18, wherein a film thickness of a portion corresponding to each of said embedded insulators under said select gate electrode is equal to or larger than a film thickness of a portion isolating said first region in said embedded insulators.

20. The nonvolatile semiconductor memory device according to claim 18, wherein a film thickness of a part of a portion corresponding to each of said embedded insulators under said select gate electrode is substantially equal to a film thickness of a portion isolating said first region in said embedded insulators and less than a film thickness of a remaining part of said portion corresponding to each of said embedded insulators under said select gate electrode.

21. The nonvolatile semiconductor memory device according to claim 16, wherein a portion isolating said third region in said embedded insulators has a step.