Reduced electromigration and stressed induced migration of Cu wires by surface coating

• US 6,342,733 B1
• Filed: 07/27/1999
• Issued: 01/29/2002
• Est. Priority Date: 07/27/1999
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Stamper, Anthony Kendall, Hu, Chao-Kun, Rosenberg, Robert, Rubino, Judith Marie, Sambucetti, Carlos Juan
• Primary Examiner(s): Wilson, Allan R.
• Application Number:
  US09/361,573
• Time in Patent Office: 917 Days
• Field of Search: 257/750, 257/752, 257/762, 257/763, 257/774
• US Class Current: 257/750
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76864 Thermal treatment
• CPC Class Codes: H01L 23/53228 the principal metal being copper
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization by polishing, while providing protection against oxidation and surface, or interface, diffusion of Cu which has been identified by the inventors as the leading contributor to metal line failure by electromigration and thermal stress voiding. Also, the metal layer increases the adhesion strength between the Cu and dielectric so as to further increase lifetime and facilitate process yield. The free surface is a direct result of the CMP (chemical mechanical polishing) in a damascene process or in a dry etching process by which Cu wiring is patterned. It is proposed that the metal capping layer be deposited by a selective process onto the Cu to minimize further processing. We have used electroless metal coatings, such as CoWP, CoSnP and Pd, to illustrate significant reliability benefits, although chemical vapor deposition (CVD) of metals or metal forming compounds can be employed.

Claims

1. A structure comprising:

a layer of dielectric on a substrate,

at least one trench formed in said dielectric on said substrate,

a metal liner formed in said trench,

a conductor selected from the group consisting of copper and copper alloys on said liner filling said trench,

a planarized upper surface of said conductor with the upper surface of said layer of dielectric, and

a conductive film over said upper surface of said conductor only,

said conductive film having a thickness in the range from 1 to 20 nm and forming a metal to metal chemical and metallurgical bond to provide high electromigration resistance and high resistance to thermal stress voiding and whereby said upper surface of said conductor and said upper surface of said layer of dielectric remain within 20 nm of being co-planar,

said conductive film selected from the group consisting of CoWP, CoSnP, CoP, CoB, CoSnB, CoWB and In whereby said upper surface of said conductor is protected from oxidation and corrosion.

2. The structure of claim 1 wherein said conductive film has a thickness in the range from 1 to 10 nm.

3. The structure of claim 1 further including an insulating cap dielectric layer over said conductive film on said conductor and said layer of dielectric, said layer of dielectric within 20 nm of being planar.

4. The structure of claim 3 wherein said insulating dielectric cap layer is selected from the group consisting of silicon nitride, silicon oxide, insulating compounds of SICOH having dielectric constants less than 3.2, diamond-like carbon, fluorinated diamond like carbon and poly (Arylene ether).

5. The structure of claim 1 wherein said substrate is selected from the group consisting of silicon, silicon-germanium, SOI, and gallium arsenide.

6. A structure comprising:

a patterned conductor on a substrate,

a conductive film over said surface of said conductor only, said conductive film having a thickness in the range from 1 to 20 nm and forming a metal to metal metallurgical bond to provide high electromigration resistance and high resistance to thermal stress voiding,

said conductive film selected from the group consisting of CoWP, CoSnP, CoP, CoB, CoSnB, CoWB and In whereby said upper surface of said conductor is protected from oxidation and corrosion.

7. The structure of claim 6 wherein said conductive film has a thickness in the range from 1 to 10 nm.

8. The structure of claim 6 further including an insulating cap dielectric layer over said conductive film on said conductor.

9. The structure of claim 8 wherein said insulating dielectric cap layer is selected from the group consisting of silicon nitride, silicon oxide, insulating compounds of SICOH having dielectric constants less than 3.2, diamond-like carbon, fluorinated diamond like carbon and poly (Arylene ether).

10. The structure of claim 6 wherein said conductor is selected from the group consisting of copper and copper alloys.

11. The structure of claim 6 wherein said substrate is selected from the group consisting of silicon, silicon-germanium, SOI, and gallium arsenide.