Method of determining a scaling factor

• US 6,343,303 B1
• Filed: 05/19/1999
• Issued: 01/29/2002
• Est. Priority Date: 05/20/1998
• Status: Expired due to Fees

• Current Assignee: Zarlink Semiconductor Inc. (Microchip Technology Incorporated)
• Original Assignee: Mital Corporation
• Inventors: Nevranmont, Adam
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US09/314,104
• Time in Patent Office: 986 Days
• Field of Search: 708/208, 708/200, 341/99
• US Class Current: 708/208
• CPC Class Codes: G06F 5/01 for shifting, e.g. justifying, scaling, normalising digital stores in which the information is moved stepwise, e.g. shift-registers G11C19/00; digital stores in which the information circulates G11C21/00

Abstract

A method of determining the scaling factor for a signed n bit binary number, where n=2^e, includes the steps of dividing the number into a plurality of subgroups of at least two bits each; providing a plurality of subunits holding the respective subgroups of bits; and arranging the subunits in a hierarchical tree structure of units. Each unit of a superior level receives inputs from units of a lower level, and each unit produces first, second and third output signals. The first output signal represents the most significant bit of the units in the associated hierarchy, the second signal indicates whether the bits in the associated hierarchy have the same value, and the third signal is an i-bit number representing the number of places less one that the bits in the associated hierarchy can be shifted. The index i is the same as the associated level in the hierarchy.

Claims

1. A method of determining the scaling factor for a signed n bit binary number, where n=2^e, comprising the steps of:

a) dividing the number into a plurality of subgroups of at least two bits each;

b) providing a plurality of subunits holding said respective subgroups of bits; and

c) arranging said subunits in a hierarchical tree structure of units, with each unit of a superior level receiving inputs from units of a lower level, each unit producing first, second and third output signals, said first output signal representing the most significant bit of said units in the associated hierarchy, said second signal indicating whether the bits in the associated hierarchy have the same value, and said third signal being an i-bit number representing the number of places less one that the bits in the associated hierarchy can be shifted, the index i being the same as the associated level in the hierarchy.

2. A method as claimed in claim 1 wherein said first signal is propagated up the hierarchy from each level to the next most superior level.

3. A method as claimed in claim 2, wherein second signal is the result of performing an exclusive NOR operation on the first signals of the inputs in the current level of the hierarchy and performing an AND operation with the second signals in the current level of the hierarchy or the equivalent in opposite logic.

4. A method as claimed in claim 2, wherein said third signal (VAL) is the result of performing the following logic operation:

5. A circuit for determining the scaling factor for a signed n bit binary number, where n=2^e, comprising:

a) a register for storing said number, said register being divided into a plurality of subunits of at least two bits each; and

b) a hierarchical tree structure of units with said subunits forming the lowest level thereof, and each unit of a superior level receiving inputs from units of a lower level, each unit producing first, second and third output signals, said first output signal representing the most significant bit of said units in the associated hierarchy, said second signal indicating whether the bits in the associated hierarchy have the same value, and said third signal being an i-bit number representing the number of places less one that the bits in the associated hierarchy can be shifted, the index i being the same as the associated level in the hierarchy.

6. A circuit as claimed in claim 5, comprising circuitry for propagating the first signal up the hierarchy so that the first signal is the same for all levels.

7. A circuit as claimed in claim 6, comprising in each unit an exclusive NOR gate receiving the first signal from adjacent units at an inferior level and an AND gate for producing said second signal from the output of said exclusive NOR gate the second signal inputs from the inferior level or the equivalent in opposite logic.

8. A circuit as claimed in claim 7, comprising a multiplexer for producing said third signal from the most significant said second signal from the inferior level and the output of said exclusive NOR gate and from the third signal from the inferior level or the equivalent in opposite logic.

9. A circuit as claimed in claim 8, wherein said mulitplexer produces said third signal in accordance with the logic:

10. A digital signal processor in including a circuit for determining the scaling factor for a signed n bit binary number, where n=2^e as claimed in claim 5.