Large-scale integrated circuit and method for testing a board of same

• US 6,343,365 B1
• Filed: 11/04/1998
• Issued: 01/29/2002
• Est. Priority Date: 02/17/1998
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Ito, Hiroo, Matsuzawa, Hajime
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): LAMARRE, GUY J
• Application Number:
  US09/185,636
• Time in Patent Office: 1,182 Days
• Field of Search: 714/724, 714/726-728, 714/729, 714/731, 714/738, 714/735, 714/30, 714/33, 714/733, 714/736.7, 714/814, 714/802, 714/739, 714/730-734, 714/725, 714/56, 714/43, 326/57, 326/16, 326/39-40, 326/126-127, 324/769, 324/158.1, 324/73.1, 324/763, 716/3, 365/200-201, 710/100, 327/199, 340/825.5, 368/113, 368/118, 368/120, 377/70, 377/47, 377/54, 377/75, 377/77, 370/462
• US Class Current: 714/726
• CPC Class Codes: G01R 31/318558 Addressing or selecting of subparts of the device under test
• CPC Class Codes: G01R 31/318586 with partial scan or non-scannable parts

Abstract

In a large-scale integrated circuit, a scan path is divided between an I/O scan path that is formed by a series connection between only flip-flops that are in a region near an I/O pin and an internal scan path that is formed by a series connection between other flip-flops. A selector has one of its inputs connected to another end of the I/O scan path and to one end of the internal scan path, another of its inputs connected to another end of the internal scan path, and its output connected to a scan out. This selector, based on a test mode signal, selects either all scan paths or only the I/O scan path.

Claims

1. A large-scale integrated circuit having a structure that has a scan path formed by a series connection of flip-flops, said scan path being divided into an I/O scan path formed by a series connection of only flip-flops, each of which is in a region near the respective I/O pins, and an internal scan path formed by a series connection of flip-flops other than those as afore-mentioned, and said large-scale integrated circuit further comprising a selector that selects either all scan paths or only said I/O scan path.

2. The circuit as claimed in claim 1, wherein said I/O pins constitute I/O pins for a single large-scale integrated circuit chip, and

wherein said I/O scan path and said internal scan path are contained in said single large-scale integrated circuit chip.

3. A large-scale integrated circuit having a structure that has a scan path formed by a series connection of flip-flops, said scan path being divided into an I/O scan path formed by a series connection of only flip-flops, each of which is in a region near the respective I/O pins, and an internal scan path formed by a series connection of flip-flops, other than those as afore-mentioned, and said large-scale integrated circuit further comprising a selector, one input of which is connected to the other end of said I/O scan path and to one end of said internal scan path, another input of which is connected to another end of said internal scan path, and an output of which is connected to a scan out, said selector, based on a test mode signal, selecting either all scan paths or only said I/O scan path.

4. The circuit as claimed in claim 3, wherein said I/O pins constitute I/O pins for a single large-scale integrated circuit chip, and

wherein said I/O scan path and said internal scan path are contained in said single large-scale integrated circuit chip.

5. A large-scale integrated circuit having a structure that has a scan path formed by a series connection of flip-flops, said scan path being divided into an I/O scan path formed by a series connection of only flip-flops, each of which is in a region near the respective I/O pins, and an internal scan path formed by a series connection of flip-flops, other than those as afore-mentioned, and said large-scale integrated circuit further comprising a selector, one input of which is connected to a scan in and to one end of said internal scan path, another input of which is connected to another end of said internal scan path, and an output of which is connected to one end of said I/O scan path, said selector, based on a test mode signal, selecting either all scan paths or only said I/O scan path.

6. The circuit as claimed in claim 5, wherein said I/O pins constitute I/O pins for a single large-scale integrated circuit chip, and

wherein said I/O scan path and said internal scan path are contained in said single large-scale integrated circuit chip.

7. A large-scale integrated circuit having a structure that has a scan path formed by a series connection of flip-flops, said scan path being divided into an I/O scan path formed by a series connection of only flip-flops, each of which is in a region near the respective I/O pins, that are in a region near an I/O pin, and first and second internal scan paths that are formed by a series connection of flip-flops, other than those as afore-mentioned, said large-scale integrated circuit further comprising a first selector, one input of which is connected to a scan in and to one end of said first internal scan path, another input of which is connected to another end of said first internal scan path, and an output of which is connected to one end of said I/O scan path, and a second selector, one input of which is connected to another end of said I/O scan path and to one end of said second internal scan path, another input of which is connected to another end of said second internal scan path, and an output of which is connected to a scan out, said first and second selectors, based on a test mode signal, selecting either all scan paths or only said I/O scan path.

8. The circuit as claimed in claim 7, wherein said I/O pins constitute I/O pins for a single large-scale integrated circuit chip, and

wherein said I/O scan path, and said first internal scan path, and said second internal scan path are contained in said single large-scale integrated circuit chip.

9. A large-scale integrated circuit having a structure that has a scan path formed by a series connection of flip-flops, said scan path being divided into first and second I/O scan paths formed by only flip-flops, each of which is in a region near the respective I/O pins, and an internal scan path formed by a series connection of flip-flops, other than those as afore-mentioned, said large-scale integrated circuit further comprising a selector, one input of which is connected to another end of said first I/O scan path and to one end of said internal scan path, another input of which is connected to another end of said internal scan path, and an output of which is connected to one end of said second I/O scan path, said selector, based on a test mode signal, selecting either all scan paths or only said I/O scan paths.

10. The circuit as claimed in claim 9, wherein said I/O pins constitute I/O pins for a single large-scale integrated circuit chip, and

wherein said first I/O scan path, said second I/O scan path, and said internal scan path are contained in said single large-scale integrated circuit chip.

11. A method of performing a board test of a plurality of large-scale integrated circuits having a structure having a scan path formed by a series connection of flip-flops, said scan path being divided into an I/O scan path formed by a series connection of only flip-flops, each of which is in a region near the respective I/O pins, and an internal scan path formed by a series connection of flip-flops, other than those as afore-mentioned, whereby connection is made between I/O pins of said plurality of integrated circuits, and further whereby a selector is used to select only said I/O scan path, test data being scanned into and out of said I/O scan paths of said plurality of integrated circuits so as to perform sending and receiving of data between said I/O scan paths, thereby verifying a connection between said large-scale integrated circuits.

12. The method as claimed in claim 11, wherein said I/O pins constitute I/O pins for a single large-scale integrated circuit chip, and

wherein said I/O scan path and said internal scan path are contained in said single large-scale integrated circuit chip.

13. A method of performing a board test of a plurality of large-scale integrated circuits having a structure having a scan path formed by a series connection of flip-flops, said scan path being divided into an I/O scan path formed by a series connection of only flip-flops, each of which is in a region near the respective I/O pins, and an internal scan path formed by a series connection of flip-flops, other than those as afore-mentioned, whereby connection is made between I/O pins of said plurality of integrated circuits and a test mode signal is applied from outside, so that test data is scanned into and out of said I/O scan path of each of said plurality of integrated circuits, so as to perform sending and receiving of data between said I/O scan paths, thereby verifying a connection between said plurality of large-scale integrated circuits.

14. The method as claimed in claim 13, wherein said I/O pins constitute I/O pins for a single large-scale integrated circuit chip, and

wherein said I/O scan path and said internal scan path arc contained in said single large-scale integrated circuit chip.

15. A large-scale integrated circuit formed in a large-scale integrated circuit chip, comprising:

a I/O scan path formed by a series connection of I/O scan path flip-flops contained in said large-scale integrated circuit chip;

an internal scan path formed by a series connection of internal scan path flip-flops contained in said large-scale integrated circuit chip;

I/O pins for inputting data to and outputting data from said large-scale integrated circuit chip, wherein said I/O scan path flip flops are disposed in a region near the said I/O pins; and

a selector that selects either a combined scan path, which comprises said I/O scan path and said internal scan path, or only said I/O scan path.

16. The large-scale integrated circuit, as claimed in claim 15, wherein a first selector input of said selector is connected to a first end of said I/O scan path and a first end of said internal scan path,

wherein a second selector input of said selector is connected to a second end of said internal scan path,

wherein a selector output of said selector is connected to a scan output terminal, and

wherein said selector selectively connects said first selector input to said selector output and selectively connects said second selector input to said selector output based on a test mode signal.

17. The large-scale integrated circuit, as claimed in claim 15, wherein a first selector input of said selector is connected to a first end of said internal scan path and a scan input terminal,

wherein a second selector input of said selector is connected to a second end of said internal scan path,

wherein a selector output of said selector is connected to a first end of said I/O scan path, and

wherein said selector selectively connects said first selector input to said selector output and selectively connects said second selector input to said selector output based on a test mode signal.

18. A large-scale integrated circuit formed in a large-scale integrated circuit chip, comprising:

a I/O scan path formed by a series connection of I/O scan path flip-flops contained in said large-scale integrated circuit chip;

a first internal scan path formed by a series connection of first internal scan path flip-flops contained in said large scale integrated circuit chip;

a second internal scan path formed by a series connection of second internal scan path flip-flops contained in said large-scale integrated circuit chip;

I/O pins for inputting data to and outputting data from said large-scale integrated circuit chip, wherein said I/O scan path flip flops arc disposed in a region near the said I/O pins;

a first selector, wherein a first selector input of said first selector is connected to a first end of said first internal scan path and a scan input terminal, wherein a second selector input of said first selector is connected to a second end of said first internal scan path, wherein a selector output of said first selector is connected to a first end of said I/O scan path; and

a second selector, wherein a first selector input of said second selector is connected to a first end of said second internal scan path and a second end of said I/O scan path, wherein a second selector input of said second selector is connected to a second end of said second internal scan path, wherein a selector output of said second selector is connected to a scan output terminal.

19. The circuit as claimed in claim 18, wherein said first selector selectively connects said first selector input of said first selector to said selector output of said first selector,

wherein said first selector selectively connects said second selector input of said first selector to said selector output of said first selector,

wherein said second selector selectively connects said first selector input of said second selector to said selector output of said second selector, and

wherein said second selector selectively connects said second selector input of said second selector to said selector output of said second selector.

20. A large-scale integrated Circuit formed in a large-scale integrated circuit chip, comprising:

a first I/O scan path formed by a series connection of first I/O scan path flip-flops contained in said large-scale integrated circuit chip;

a second I/O scan path formed by a series connection of second I/O scan path flip-flops contained in said large-scale integrated circuit chip;

an internal scan path formed by a series connection of internal scan path flip-flops contained in said large-scale integrated circuit chip;

I/O pins for inputting data to and outputting data from said large-scale integrated circuit chip, wherein said first and second I/O scan path flip flops are disposed in a region near the said I/O pins; and

a selector,

wherein a first selector input of said selector is connected to a first end of said first I/O scan path and a first end of said internal scan path,

wherein a second selector input of said selector is connected to a second end of said internal scan path,

wherein a selector output of said selector is connected to a first end of said second I/O path, and

wherein said selector selectively connects said first selector input to said selector output and selectively connects said second selector input to said selector output.