Methods of manufacture of crown or stack capacitor with a monolithic fin structure made with a different oxide etching rate in hydrogen fluoride vapor

• US 6,344,392 B1
• Filed: 11/16/1998
• Issued: 02/05/2002
• Est. Priority Date: 11/16/1998
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Vanguard International Semiconductor Corporation
• Inventors: Liaw, Ing-Ruey
• Primary Examiner(s): Meier, Stephen D.
• Assistant Examiner(s): Thomas, Toniae M.
• Application Number:
  US09/192,457
• Time in Patent Office: 1,177 Days
• Field of Search: 257/306, 257/307, 257/308, 257/309, 438/397, 438/254, 438/239, 438/253, 438/255, 438/396, 438/398
• US Class Current: 438/254
• CPC Class Codes: H01L 28/87 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor

Abstract

A capacitor core is formed on a semiconductor device with a first conductive layer in contact with a plug. A mold is formed from a stack of alternately doped and undoped silicon dioxide layers on the sublayer with the stack comprising a bottom layer formed on top of the sublayer and each additional layer in the stack formed on a previous one of the layers in the stack. Pattern the silicon dioxide layers in the mold which are alternatingly doped and undoped to form an intercore, capacitor-core-shaping cavity in the stack of silicon dioxide layers reaching down through the stack to be bottom of the stack. Then perform differential etching of the silicon dioxide layers in the mold. Form undercut edges in the doped silicon dioxide layers with the undoped silicon dioxide layers having cantilevered ribs projecting from the stacks into the cavity to complete the mold. Deposit a bulk or a thin film second monolithic conductive layer into the cavity to form a monolithic capacitor core with counterpart cantilevered ribs.

Claims

1. A process comprising steps in the sequence as follows:

form a conductive sublayer directly on top of each of a plurality of conductive plugs and a glass planarizing insulating layer which covers gate electrode/conductor stacks having spacers on the sides thereof, with the conductive plugs in direct contact with the silicon dioxide spacers,

form a plurality of molds on the conductive sublayer, the plurality of molds comprising a stack of silicon dioxide layers which are alternatingly undoped, doped with a dopant, and undoped with the stack comprising a bottom layer formed on top of the conductive sublayer and each additional layer in the stack formed on a previous one of the layers in the stack,

pattern the silicon dioxide layers in the plurality of molds which are alternatingly doped and undoped to form intercore, capacitor-core-shaping cavities in the stack, reaching down through the stack to the conductive sublayer at the bottom of the stack,

perform a differential etch of the silicon dioxide layers in the plurality of molds forming undercut edges in the doped silicon dioxide layers with the undoped silicon dioxide layers having cantilevered ribs projecting from the stack into the cavities to complete the plurality of molds,

deposit a conductive core layer into the cavities forming a hollow capacitor cores with counterpart cantilevered ribs with a complementary pattern to the plurality of molds and the capacitor cores each each having a top surface,

fill the hollow capacitor cores with photoresist,

polish the hollow capacitor cores to remove the top surface of the capacitor cores,

remove the photoresist and the plurality of molds, and

then, after removal of the molds, perform an etch of the sublayer to separate the monolithic capacitor cores from adjacent monolithic capacitor cores thereby exposing the planarizing glass insulating layer.

2. The process of claim 1 including the steps as follows;

the planarizing insulating layer comprises glass which covers gate electrode/conductor stacks having spacers on the sides thereof, with the conductive plugs in direct contact with the silicon dioxide spacers,

form the conductive core layer of a material selected from the group consisting of aluminum, copper, tungsten and titanium nitride,

perform the differential etch of the silicon dioxide layers in the plurality of molds with a combination of hydrogen fluoride vapor and water vapor, and

remove the plurality of molds with a buffered oxide etching solution.

3. The process of claim 1 including the steps as follows:

dope with boron and phosphorus dopant,

perform the differential etch of said silicon dioxide layers in the plurality of molds with a combination of hydrogen fluoride vapor and water vapor, and

remove the plurality of molds with a buffered oxide etching solution.

4. The process of claim 1 including the steps as follows:

fill the cavities with the hollow capacitor cores,

perform the differential etch of said silicon dioxide layers in the plurality of molds with a combination of hydrogen fluoride vapor and water vapor, and

remove the plurality of molds with a buffered oxide etching solution.

5. The process of claim 1 including the steps as follows:

fill the cavities with the hollow capacitor cores,

dope boron and phosphorus dopant, and

perform the differential etch of said silicon dioxide layers in away the plurality of molds with a combination of hydrogen fluoride vapor and water vapor, and

remove the plurality of molds with a buffered oxide etching solution.

6. The process of claim 1 including the steps as follows:

form the capacitor cores as monolithic capacitor cores, and

polish the monolithic capacitor cores by a Chemical Mechanical Planarization (CMP) process which removes a top undoped layer of the plurality of molds whereby each of the monolithic capacitor cores has a flat upper surface with a rib located at the top of each of the monolithic capacitor cores.

7. A process comprising steps in the sequence as follows:

form a conductive sublayer directly on a top of a plurality of conductive plugs and a glass planarizing insulating layer,

form a plurality of molds over said plugs from a stack of silicon dioxide layers which are alternatingly doped and undoped on the conductive sublayer with the stack comprising a bottom layer formed on top of the conductive sublayer and each additional layer in the stack formed on a previous one of the layers in the stack,

pattern the silicon dioxide layers in the plurality of molds which are alternatingly doped and undoped to form intercore, capacitor-core-shaping cavities in the stack reaching down through the stack to the conductive sublayer at the bottom of the stack,

perform a differential etch of the silicon dioxide layers in the plurality of molds forming undercut edges in the doped silicon dioxide layers with the undoped silicon dioxide layers having cantilevered ribs projecting from the stack into the cavities to complete the plurality of molds,

deposit a thin conductive layer into the cavities to form a thin capacitor cores with counterpart cantilevered ribs with a complementary pattern to the plurality of molds and each of the capacitor cores having an inner cavity and a top surface,

fill the inner cavities with photoresist,

polish the capacitor cores to remove the top surface of the capacitor cores,

then remove the photoresist and the plurality of molds, and

then, after removal of the molds, perform an etch of the sublayer to separate the monolithic capacitor cores from adjacent monolithic capacitor cores thereby exposing the planarizing glass insulating layer.

8. The process of claim 7 including the steps as follows:

form the thin capacitor cores of a material selected from the group consisting of aluminum, copper, tungsten and titanium nitride, and

etch away the plurality of molds.

9. The process of claim 7 including the steps as follows:

the dopant comprising boron and phosphorus, and

etch away the plurality of molds.

10. The process of claim 7 including the steps as follows:

form the plurality of molds each having a mold top,

form the capacitor cores as monolithic capacitor cores each having a core top juxtaposed with the mold top,

polish each mold top and each core top by a Chemical Mechanical Planarization (CMP) process which removes a top undoped layer of the plurality of molds and a corresponding top portion of each of the monolithic capacitor cores leaving a flat upper surface with a rib located on top of each of the monolithic capacitor cores.

11. A process comprising steps in the sequence as follows:

form a conductive sublayer in contact with a plurality of conductive plugs formed in a planarizing insulating layer,

form a plurality of molds from a stack of silicon dioxide layers which are alternatingly doped with a dopant and undoped on the conductive sublayer with the stack comprising a bottom layer formed on top of the sublayer and each additional layer in the stack formed on a previous one of the layers in the stack and including a top mold layer,

pattern the silicon dioxide layers to form intercore, capacitor-core-shaping cavities in the stack of silicon dioxide layers reaching down through the stack to the conductive sublayer at the bottom of the stack,

etch the silicon dioxide layers differentially in the plurality of molds forming undercut edges in the doped silicon dioxide layers with the undoped silicon dioxide layers having cantilevered ribs projecting from the stack into the cavities to complete the plurality of molds,

deposit a thin conductive layer forming a thin capacitor cores in the cavities with counterpart cantilevered ribs with a complementary pattern to the plurality of molds and the capacitor cores having a top capacitor cores surface leaving inner cavities,

deposit a layer filling the inner cavities;

polish to remove the top mold layer and the top capacitor cores surface; and

remove the plurality of molds.

12. The process of claim 11 including removing the plurality of molds by etching with a buffered oxide etching solution.

13. The process of claim 11 including the steps as follows:

the dopant comprising boron and phosphorus, and

differentially etching said silicon dioxide layers in the plurality of molds with a combination of hydrogen fluoride vapor and water vapor.

14. The process of claim 11 including the steps as follows:

polish the capacitor cores by a Chemical Mechanical Planarization (CMP) process which removes a top undoped layer of the plurality of molds whereby the thin capacitor cores has a flat upper surface with a rib located on top of the thin capacitor cores, and

etch the sublayer to separate the thin capacitor cores from adjacent capacitor cores.

15. The process of claim 11 including the steps as follows:

etch away the plurality of molds with a buffered oxide etching solution,

the thin conductive cores being composed of a material selected from the group consisting of aluminum, copper, tungsten, and titanium nitride, and

the thin conductive layer having a thickness from about 500 Å

to about 1,000 Å

.

16. The process of claim 11 including the steps as follows:

providing the dopant comprising boron and phosphorus, and

etch away the plurality of molds with a buffered oxide etching solution,

form the thin conductive layer of a material selected from the group consisting of aluminum, copper, tungsten, and titanium nitride, and

form the thin conductive layer with a thickness from about 500 Å

to about 1,000 Å

.

17. The process of claim 11 including the steps as follows:

form the thin conductive cores as monolithic capacitor cores,

polish the monolithic capacitor cores by a Chemical Mechanical Planarization (CMP) process which removes a top undoped layer of the plurality of molds whereby each of the monolithic capacitor cores has a flat upper surface with a rib located on top of each of the monolithic capacitor cores,

etch the sublayer to separate each of the monolithic capacitor cores from adjacent monolithic capacitor cores,

form each of the monolithic capacitor cores from a material selected from the group consisting of aluminum, copper, tungsten, and titanium nitride, and

form each of the monolithic capacitor cores with a thickness from about 500 Å

to about 1,000 Å

.

18. A process comprising steps in the sequence as follows:

form a conductive sublayer in contact with a plurality of conductive plugs formed in a planarizing insulating layer, by steps in the sequence as follows;

form a plurality of molds from a stack of silicon dioxide layers which are alternatingly doped and undoped on the conductive sublayer with the stack comprising a bottom layer formed on top of the conductive sublayer and each additional layer in the stack formed on a previous one of the layers in the stack including an undoped top silicon dioxide layer on top of the stack, with doped silicon dioxide layers comprising BPSG layers,

pattern the silicon dioxide layers in the plurality of molds which are alternatingly doped and undoped to form intercore, capacitor-core-shaping cavities in the stack reaching down through the stack to the conductive sublayer at the bottom of the stack,

differentially etch the silicon dioxide layers in the plurality of molds forming undercut edges in the doped silicon dioxide layers with the undoped silicon dioxide layers having cantilevered ribs projecting from the stack into the cavities to complete the plurality of molds,

deposit a thin conductive layer into the cavities to form a thin capacitor cores with counterpart cantilevered ribs with a complementary pattern to the plurality of molds and the capacitor cores having inner cavities and a top surface, each of the monolithic capacitor cores being formed of a material selected from the group consisting of aluminum, copper, tungsten, and titanium nitride and each of the monolithic capacitor cores having a thickness from 500 Å

to 1,000 Å

,

deposit photoresist into the inner cavities,

polish away the undoped top silicon dioxide layer of the plurality of molds and the top surface of the capacitor cores by a Chemical Mechanical Planarization (CMP) process which removes the top undoped layer of the plurality of molds whereby the thin capacitor cores has a flat upper surface with a rib located on top of the thin capacitor cores,

remove the photoresist and etch away the plurality of molds with a combination of hydrogen fluoride vapor and water vapor, and

etch back the sublayer to separate the thin capacitor cores from adjacent capacitor cores.