Guardring DRAM cell

• US 6,344,672 B2
• Filed: 05/30/2001
• Issued: 02/05/2002
• Est. Priority Date: 12/28/1998
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Huffman, James D.
• Primary Examiner(s): Epps, Georgia
• Assistant Examiner(s): TRA, TUYEN Q
• Application Number:
  US09/870,285
• Publication Number:
  US 20010038487A1
• Time in Patent Office: 251 Days
• Field of Search: 359/248, 359/291, 359/295, 359/245, 359/290, 359/226, 359/224, 359/298, 257/296, 257/297, 257/298, 257/299, 257/300, 257/301, 257/302, 257/303, 257/304, 257/305, 257/306, 257/307, 257/308, 257/309, 257/310, 438/253-254, 438/396-398
• US Class Current: 257/296
• CPC Class Codes: G02B 26/0841 the reflecting element being moved or deformed by electrostatic means

Abstract

An improved memory cell (600) for use in a high-intensity light environment. The memory (600) comprises a substrate (616) capable of generating photocarriers when exposed to radiant energy, at least one transistor (602), at least one capacitor (604), and address node (610) electrically connecting the transistor (602) and the capacitor (604), and an active collector region (626). The active collector region (626) is fabricated in the substrate (616) in a position to allow the active collector region (626) to recombine photocarriers traveling through the substrate (616) thus preventing the photocarriers from reaching the address node (610).

Claims

1. A memory cell comprising:

a substrate, said substrate capable of generating photocarriers when exposed to radiant energy;

at least one transistor;

at least one capacitor, said at least, one capacitor comprising a first plate and a second plate;

an address node electrically connecting said first plate of said at least one capacitor to said at least one transistor; and

an active collector region fabricated in said substrate in a position to allow said active collector region to block photocarriers traveling through said substrate from reaching said address node.

2. The memory cell of claim 1, wherein said active collector region encircles said address node.

3. The memory cell of claim 1, wherein said active collector region is a doped semiconductor region.

4. The memory cell of claim 1, wherein said active collector region is an n-doped semiconductor region.

5. The memory cell of claim 1, wherein said active collector region is at least 1.5 μ

m deep.

6. The memory cell of claim 1, wherein said active collector region is positively biased.

7. The memory cell of claim 1, wherein said first plate is polysilicon.

8. The memory cell of claim 1, wherein said first plate is negatively biased relative to said second plate.

9. The memory cell of claim 1, wherein said second plate is a depletion layer formed in said active collector region.

10. The memory cell of claim 1, wherein said first plate encircles said address node.

11. The memory cell of claim 1, wherein said first plate is comprised of two polysilicon regions.